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ASC Bridge Board 

 

Evaluation Board User Guide 

 

 

© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at 

www.latticesemi.com/legal

.  

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-EB-02025-2.0 

 

23 

Table D.4. Miscellaneous – ECP5 Versa Development Board and ASC Bridge Board Connections 

Bridge Board 
Signal Name 

J2 Pin 
X4 Pin 

J3 Pin 
X3 Pin 

ECP5 Versa Board 
Signal Name 

ECP5 Ball 

Project Designer 
Signal Name 

I2C_SDA

1

 

16 

— 

EXPCON_IO13 

B10 

SCL 

I2C_SCL

1

 

18 

— 

EXPCON_IO15 

E12 

SDA 

I2C_WRITE_EN

2

 

32 

— 

EXPCON_IO23 

D16 

— 

PB1 (SW1) 

15 

— 

EXPCON_IO12 

A9 

User Defined 

PB2 (SW2) 

21 

— 

EXPCON_IO16 

B15 

User Defined 

MANDATORY_RESET 

28 

— 

EXPCON_IO20 

A16 

User Defined 

FAN1_PWM 

— 

19 

EXPCON_IO40 

C7 

User Defined 

FAN1_TACH 

— 

20 

EXPCON_IO45 

C6 

User Defined 

FAN2_PWM 

— 

17 

EXPCON_IO42 

D8 

User Defined 

FAN2_TACH 

— 

18 

EXPCON_IO43 

E8 

User Defined 

FAN3_PWM 

— 

15 

EXPCON_IO44 

B8 

User Defined 

FAN3_TACH 

— 

16 

EXPCON_IO41 

C8 

User Defined 

EXPCON_OSC

3

 

— 

29 

EXPCON_OSC 

— 

— 

EXPCON_CLKIN 

— 

31 

EXPCON_CLKIN 

A10 

— 

EXPCON_CLKOUT 

— 

33 

EXPCON_CLKOUT 

E11 

— 

HPE_RESOUT# 

 

HPE_RESOUT# 

A8 

— 

EXPCON_IO0 

 

EXPCON_IO0 

A12 

User Defined 

EXPCON_IO2 

 

EXPCON_IO2 

B13 

User Defined 

EXPCON_IO14 

17 

— 

EXPCON_IO14 

D12 

User Defined 

EXPCON_IO17 

23 

— 

EXPCON_IO17 

C15 

User Defined 

CARDSEL# 

38 

— 

CARDSEL# 

A7 

User Defined 

Notes: 

 

SDA and SCL signal mapping shown are for SW3 (I

2

C Select) in the MachXO3 position. 

 

If I2C_WRITE_EN is not used, remove R4 on the ASC Breakout Boards to isolate their GPIO1 (LED1) signals; the I2C_WRITE_EN 
signal is bussed to all three ASC connectors on the ASC Bridge board. 

 

ispCLOCK5406D BANK_2P (U13 pin 27). 

 

 

Содержание ASC Bridge Board

Страница 1: ...ASC Bridge Board Evaluation Board User Guide FPGA EB 02025 2 0 September 2018...

Страница 2: ...Female Header 8 8 J6 J7 and J13 D SUB25 Connector 8 9 J1 Male Header 11 10 J16 Fan 1 Header 12 11 J21 Fan 2 Header 12 12 J19 Fan 3 Header 12 13 Push Buttons 13 14 LED Indicators 13 15 Demonstration D...

Страница 3: ...Table 10 1 Fan 1 Header Connection 12 Table 11 1 Fan 2 Header Connection 12 Table 12 1 Fan 3 Header Connection 12 Table 13 1 Momentary Push Buttons 13 Table C 1 ASC1 J4 MachXO3 9400 Development Board...

Страница 4: ...uct names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice 4 FPGA EB 02025 2 0 Acronyms in This Docume...

Страница 5: ...SC B EVN and on the Lattice web site the product name is L ASC10 Breakout Board The ASC Bridge Board does not contain any programmable logic nor does it have a USB connector for power or programming T...

Страница 6: ...ugh hole prototype area Three fan connectors with PWM pulse width modulation drive circuitry Two tactile push buttons Connectors for up to three ASC Breakout Boards Expansion header for additional FPG...

Страница 7: ...by either the MachXO3 9400 Development Board or the ECP5 Versa Development Board Depending on your design requirement the 5 V and 12 V power can be applied through the ASC Breakout Board after the Hot...

Страница 8: ...om either the MachXO3 9400 Development Board or the ECP5 Versa Development Board to the ASC Bridge Board The female header carries both signal and power The connections for J2 and J3 are listed in App...

Страница 9: ...erein are subject to change without notice FPGA EB 02025 2 0 9 Table 8 2 J13 D SUB 25 Connection J13 Header Pin Number ASC Pin Function Header Connection Header Pin Number 1 GND 2 WDAT J2 11 3 RDAT J2...

Страница 10: ...ein are subject to change without notice 10 FPGA EB 02025 2 0 Table 8 3 J7 D SUB 25 Connection J7 Header Pin Number ASC Pin Function Header Connection Header Pin Number 1 GND 2 WDAT J2 27 3 RDAT J2 31...

Страница 11: ...Pin Number Silkscreen Name MachXO3 9400 ECP5 45 FPGA Board Signal Name Ball Port Ball Port 1 3 3 V 2 2 5 V 3 N C 4 EXPCON_OSC Note 1 Note 2 EXPCON_OSC 5 EXPCON_CLKIN A10 PT23B A10 PT36A EXPCON_CLKIN...

Страница 12: ...FPGA Board Signal Name Ball Pad Ball Pad 1 PWM Switch to GND G15 PT42D D8 PT13B EXPCON_IO42 2 Fan Power 3 Fan Tachometer F15 PT42C E8 PT13A EXPCON_IO43 Note J21 pin 1 is buffered and inverted from th...

Страница 13: ...I O with a 10 k pull up resistor tied to the 3 3 V supply Depressing the button drives a logic level 0 to the device Table 13 1 Momentary Push Buttons Push Button SW MachXO3 9400 ECP5 45 FPGA Board S...

Страница 14: ...02012 L ASC10 Data Sheet FPGA DS 02038 MachXO3 9400 Development Board User Guide FPGA EB 02004 ECP5 Versa Development Board User Guide FPGA EB 02021 ASC Breakout Board User Guide FPGA EB 02023 Tempera...

Страница 15: ...nnector ASC2 Connector Fan Connector Prototype Area 3 3V in 12V in 5V in 12V in 5V in Use 4 layer routing including 3 3V and GND plane 12V and 5V supply distribution use thick trace All component shou...

Страница 16: ...Court Hillsboro Oregon 97124 Designer ASC Bridge Board B ECP5 XO3 Connection B 2 5 Tuesday July 11 2017 Title Size Project Rev Date Sheet of Lattice Semiconductor Corporation 5555 N E Moore Court Hill...

Страница 17: ...I2C_SCL 2 3 I2C_SDA 2 3 ASC1_12V_OC_SENSE 2 ASC1_12V_OC_SHUTDOWN 2 ASC1_RESET 2 ASC1_CLK_O 2 ASC1_RDAT 2 MANDATORY_RESET 2 3 Title Size Project Rev Date Sheet of Lattice Semiconductor Corporation 555...

Страница 18: ...tage Select J21 FAN2 J17 FAN3 Voltage Select J19 FAN3 J18 FAN3 Filter Select 3 3V 12V 5V 3 3V 12V 5V 12V 5V 3 3V FAN1_PWM 2 FAN2_PWM 2 FAN3_PWM 2 FAN1_TACH 2 FAN2_TACH 2 FAN3_TACH 2 Title Size Project...

Страница 19: ...J5 J8 J9 J10 J11 J12 J14 J15 Header_1x2 Molex 22284024 Male Header 2POS 100 9 3 J6 J7 J13 DSUB_25 TE Connectivity 5747842 3 Male 25Pin DSUB Connector 10 1 J16 Header_Fan_1x6 Molex 22272061 Male Heade...

Страница 20: ...ON_IO39 C20 User Defined Table C 2 ASC2 J13 MachXO3 9400 Development Board and ASC Bridge Board Connections Bridge Board Signal Name Bridge Board J2 Pin MachXO3 Board X3 Pin MachXO3 Board Signal Name...

Страница 21: ...1 15 EXPCON_IO12 C6 User Defined PB2 SW2 21 EXPCON_IO16 D8 User Defined MANDATORY_RESET 28 EXPCON_IO20 C9 User Defined FAN1_PWM 15 EXPCON_IO40 E16 User Defined FAN1_TACH 20 EXPCON_IO45 G12 User Define...

Страница 22: ...39 D9 User Defined Table D 2 ASC1 J13 ECP5 Versa Development Board and ASC Bridge Board Connections Bridge Board Signal Name Bridge Bd J2 Pin ECP5 Bd X4 Pin ECP5 Versa Board Signal Name ECP5 Ball Plat...

Страница 23: ...PCON_IO16 B15 User Defined MANDATORY_RESET 28 EXPCON_IO20 A16 User Defined FAN1_PWM 19 EXPCON_IO40 C7 User Defined FAN1_TACH 20 EXPCON_IO45 C6 User Defined FAN2_PWM 17 EXPCON_IO42 D8 User Defined FAN2...

Страница 24: ...ders The specifications and information herein are subject to change without notice 24 FPGA EB 02025 2 0 Revision History Revision 2 0 September 2018 Section Change Summary All Changed document number...

Страница 25: ...7th Floor 111 SW 5th Avenue Portland OR 97204 USA T 503 268 8000 www latticesemi com...

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