2.
Primary application properties
E20-10 —
is a module of high-speed analog-digital conversion with
USB 2.0
interface. The
product primary application properties are summed up below in short.
•
Continuous 16-bit data acquisition with frequency up to 10 MHz is provided by USB2.0
interface
.
•
4-channel architecture with one
14-bit ADC,
switch, input buffer amplifiers, filters in each
channel.
Due to input buffer amplifiers
the
dynamic switching interference effect is
impossible.
•
Each of ADC 4 channels can set in software the following input signal sub-ranges
individually per channel: ±3.0V, ±1.0V, ±0.3V.
•
Each channel has LPF (low pass filter)
3-order with frequency cut-off of 1.25 MHz
(optimal bandwidth for 4-channel ADC conversion mode and frequency is 10 MHz)
improving signal-noise-rate. Other LPF frequency cut-offs are possible (p.
•
ADC conversion frequency F
ADC
can be set within the range
from 1.00 to 10.0 MHz.
ADC
conversion frequency can be both as set in software, frequency spectrum in megahertz is
determined from the formula
F
ADC
=
30/
к
, where
к =
{3,4, 5,..., 30}, and as external with
any frequency of from 1.00 to 10.0 MHz (lower data acquisition frequency can be
reached by interframe delay setting).
•
Maximum data acquisition frequency per channel is
F
ADC
,
/
п,
where
п
=
{1,2,3,4} —
number of sampled channels.
•
In module control table the
frame —
random sequence
of channel sampling
with length of
from 1 to 256 can be programmed. Size of sampled channels will be selected cyclically
from the set size table and order of output data samples
E20-10
will comply with
channels sequence.
•
Interframe ADC sampling delay can be programmed from 0 to 65535
of ADC conversion
frequency periods .
Due to this the lower sampling frequencies can be implemented per
channel.
•
Multi-mode system has advanced synchronization modes for data acquisition and/or ADC
conversion frequency. For example, by connecting modules
E20-10
according to one
setting device - many receivers diagram
the synchronous multi-module data acquisition
system can be achieved!
•
Architecture
externally completely downloaded: downloaded
, controller firmware
can be updated. Due to this the user can update firmwares with latest versions by himself.
•
FIFO data internal buffer with size of 8 MV
buffers data saving their loss in case when
computer operating system "thinks"
(to 400 ms at an acquisition frequency of 10 MHz to
4 s at an acquisition frequency of 1 MHz).
•
Digital input-output
is presented in form of 16 input and 16 output digital TTL-compatible
lines. Digital outputs can be optional translated in
the third state.
•
Two-channel 12-bit DAC
(option) allows to set constant voltage within ±5 V under
asynchronous mode operation.
•
External device power supply output ±12 V, 35 mA
2
Under full-speed (USB1.1) mode the maximum available frequency makes 500 kHz
3
In
E20-10
revision B
4
for example, in Windows – in non-real-time (off-line) system
