manualshive.com logo in svg

L-Card E20-10, Руководство пользователя

Поделиться
Скачать
L-Card E20-10 Скачать руководство пользователя страница 27

 

 

FPGA 

Fig. 5-1. Block diagram E20-10 

 

  

Fig. 5-2. Explanation of data acquisition equipment logic interaction in E20-10 

FPGA

Статический

коммутатор 

Вход 

1

Управляемый

усилитель

Активный

ФНЧ

Канал 

1

Канал 

2

Канал 

3

Канал 

4

Вход 

2

Вход 

3

Вход 

4

конвейер

-

ное 

АЦП

Буфер

FIFO

8 MB

USB

контрол

-

лер

Преобра

-

зователь 

напряжения

Вход 

+9...+27 

В

Контрол

-

лер

AVR

Цифровой

ввод

-

вывод

ЦАП

2 

канала

USB

DI1...DI15

Выходы ЦАП

:

Выход

±12 

В

DO1...DO16

TTL-

линии

:

DAC1
DAC2

SYNC

Динами

-

ческий 

коммутатор

DI16 / START

START

DI16 

16

15

Логика 

калибровки 

и доп

. 

условий 

разрешения 

записи 

(

рев

.

В

)

данные

синхрони

-

зация

Управление 

входным 

током 

смещения

(

рев

. 

В

)

Конвейерный АЦП

Размер

кадра

Логика

калибровки

данных

(рев. В)

Логика

разрешения

записи в

буфер FIFO

Счётчик

задержки

записи

заданного

количества

кадров от

начала сбора

Логика

устранения

переполнения

(рев. В)

Счётчик

количества

собранных

кадров

данных

Логика управления

процессом сбора

данных

конвейерным АЦП

(триггер START)

Внешний старт от

перепада сигнала START

Программный старт-стоп

Старт-стоп от уровня

сигнала START (рев. В)

Стоп по количеству собранных кадров (рев.B)

Логика

разрешения

записи по

аналоговому

уровню и

переходу

через уровень

FIFO
8 MB

вх

од

вы

хо

д

Дополнительные условия

разрешения записи в буфер FIFO (рев.В)

вх

од

вы

хо

д

USB-

интерфейс

Указатель

на строку

управляющей

таблицы

Логика

управляющей

таблицы

управляющая

таблица

Входы АЦП

Аналоговые

каналы АЦП

Динамичечкий

коммутатор

Счётчик

межкадровой

задержки

Сигнал START в режиме "ведущий"

Input 1

 

Input 2

 

Input 3

 

Input 4

 

synchroniz

ation

 

data

 

Input 

 

offset  
current  
control  

(rev. В)

 

Channel 2

 

Channel 1

 

Channel 3

 

Channel 4

 

Static 

commutator

 

Controlled 

amplifier

 

Active 

 

LPF

 

 

Voltage 

converter

 

 

Dynamic 

commutator

 

DAC

 

2 channels

 

Control-

 

ler 

 

AVR

 

Digital 

input-output

 

FIFO 
buffer 

 

8 MV

 

 

USB 

controller

 

 

Pipelined 

 

ADC 

Input 

+9...+27 V

 

Output 

±12 V

 

DAC outputs:

 

TTL-lines:

 

Logic of 

calibration

 

and additional  

write enable 

conditions 

(rev.B)

 

ADC analog 

channels

 

Dynamic 

commutator

 

ADC inputs

 

Data 

calibration 

logic  

(rev. В)

 

Interframe 

delay  

counter

 

control table

 

Logic on write 

enable  

on analog level 

and transition 

though the 

level 

 

Pipelined ADC

 

Size  

frame

 

Data frame 

collected 

amount 
counter  

 

Set frame 

amount writing 

delay  

from 

acquisition 

start counter 

 

USB-

interface

 

Overflow 

elimination 

logic (rev. В)

 

input

 

input

 

out

put

 

out

put

 

Logic on write 

enable  

in FIFO 

buffer 

 

FIFO 
8 MV

 

Содержание E20-10

Страница 1: ...ESIGN MANUFACTURING DISTRIBUTION http en lcard ru en lcard ru Revision 2 01 00 October 2017 E20 10 E20 10 1 E20 10 D E20 10 D 1 E20 10 D I E20 10 D 1 I Measuring voltage converters A family of univers...

Страница 2: ...105 Moscow Varshavskoye shosse 5 block 4 bld 2 tel 495 785 95 19 fax 495 785 95 14 Internet contacts http en lcard ru E Mail Sales department en lcard ru Technical support en lcard ru E20 10 module Co...

Страница 3: ...07 2010 Paragraph 6 3 edited 2 00 10 06 2011 P 5 2 2 edited Paragraph 6 5 1 added 2 00 11 03 2012 Manor changes in documentation 2 00 12 09 2012 ADC frame is oversized up to 8192 samples Characteristi...

Страница 4: ...sbapi 20 4 2 2 USB drivers installation from LComp 20 4 3 Recognition of the module 21 4 4 Differences in USB driver of Lusbapi library 22 5 Overview of the hardware components and operation principle...

Страница 5: ...rents degrade the signal to noise ratio in your connection diagram 54 6 5 4 6 How to solve the problem if the through currents are detected 54 6 5 4 7 On disconnected ADC inputs 54 6 5 1 Digital lines...

Страница 6: ...possible keeping the same value category for data acquisition devices Revision B is assigned to new E20 10 and its manufacturing has started with 2008 Revision executed before the end of 2007 of E20...

Страница 7: ...andwidth of 1 2 MHz 2 channel DAC is available industrial design version E20 10 D 1 I ADC frequency bandwidth of 5 MHz 2 channel DAC is available industrial design version Industrial versions with alp...

Страница 8: ...10 are given The issues discussed herein will be of interest for specialists and operators When exploratory reading Chapter 5 can be missed because it describes internal architecture of module E20 10...

Страница 9: ...ce of channel sampling with length of from 1 to 256 can be programmed Size of sampled channels will be selected cyclically from the set size table and order of output data samples E20 10 will comply w...

Страница 10: ...ine conditions E20 10 can be energized from external power supply source of from 9 to 27 V Power consumption max 4 5 W6 Revision B 01 for E20 10 module has extended supply voltage range from 8 to 40 V...

Страница 11: ...calibration procedure p 5 2 5 is performed on computer by implementing of the relevant library function is performed inside E20 10 by FPGA hardware Interframe delay range p 5 2 1 0 255 ADC conversion...

Страница 12: ...mputer caused spooling by USB high delay p 5 2 4 data acquisition mandatory computer sourced restart is required restart is not required because of the required minimum number of data frames will be a...

Страница 13: ...As shown in table above revision of E20 10 module has better useful quality in variety of significant parameters in comparison with revision...

Страница 14: ...functions of internal external multi module synchronization digital asynchronous input output 2 channel asynchronous DAC option Fast E20 10 module is complemented with some slower ADC USB modules E 1...

Страница 15: ...pearance Fig 3 2 E20 10 revision appearance Appearances of E20 10 of revision B and B 01 are similar Details on revision B 01 are specified on label on body bottom wall Power supply voltage range is s...

Страница 16: ...ations power units for them and auxiliary USB cables When dealing with E20 10 the user must buy this equipment by himself in third party manufacturers The same is related to not included in delivery p...

Страница 17: ...of all Lusbapi library components is given in table below paths are specified relatively to base directory USB Lusbapi Directory Intended purpose DLL Lusbapi library including all sources import libra...

Страница 18: ...ersonal computer as tape recorder Windows 98 2000 XP Vista Developing delivering and technical support Interoptica S LLC www powergraph ru Standard software package delivered with module E20 10 includ...

Страница 19: ...it FPGA 2 00 03 and 2 00 05 firmwares are fully compatible on program library functions 2 00 06 dd 01 09 08 Updated firmware of serial E20 10 rev One channel mode sensitive data acquisition fault has...

Страница 20: ...one 4 2 USB drivers installation Procedures on USB drivers installation from libraries Lusbapi and LComp are a bit different for E20 10 module These particular differences are described in the followi...

Страница 21: ...cognized properly by operating system and is ready for further operation Indicator s color informs about E20 10 connection speed to interface USB8 red full speed green high speed You can further check...

Страница 22: ...ld USB driver Ldevusb sys To do this you should find in Device Manager the device of module E20 10 type and consecutive call of panel with its features Then on this panel you should move to bookmark D...

Страница 23: ...alert about failure of driver digital signature and propose to find drivers in Internet may be displayed Then you should move to standard information panels Hardware Update Wizard on which you should...

Страница 24: ...ate with E20 10 USB drivers both as of old version3 1 or older as new version3 2 or newer Lusbapi libraries can be simultaneously installed on computer The thing is USB driver from exactly which libra...

Страница 25: ...ently per ADC channel Measuring of own zero prior data acquisition session and program record keeping of measured value may compensate long term temperature and time ADC zero drift It should be noted...

Страница 26: ...controller controlled from AVR More advanced USB controller ISP1583 is used in revision B Both these controllers of NXP corporation support protocols of full and high speed USB interface SDRAM based F...

Страница 27: ...onverter Dynamic commutator DAC 2 channels Control ler AVR Digital input output FIFO buffer 8 MV USB controller Pipelined ADC Input 9 27 V Output 12 V DAC outputs TTL lines Logic of calibration and ad...

Страница 28: ...pon switching on the program of USB device upgraded in AVR completes procedure on connecting on USB as soon as computer connection will be detected Upon successful detecting of E20 10 by your computer...

Страница 29: ...C output is interstitial downstream of ADC pipeline but upstream of FIFO buffer write enable on analog level given amount of frames from acquisition start write delay counter collected frames amount c...

Страница 30: ...f revision supports additional permit conditions for ADC data recording in buffer memory of E20 10 on edge in selected ADC channel disabling transmission of given amount of frames from acquisition sta...

Страница 31: ...ency range of from 1 0 to 10 MHz Severe requirements are also posed on SYNC signal on off time p 7 1 3 It is natural that SYNC signal from master E20 10 complies with these requirements Note that TTL...

Страница 32: ...nt corresponds to SYNC output signal edge external slave A V SYNC line is used on input for synchronization from TTL output of external device signal with frequency of from 1 0 to 10 MHz with on off t...

Страница 33: ...sition through the given signal level in selected channel and blockage of N number of frames recording from acquisition start B 0 N 16777214 where N integral On top down transition through the given s...

Страница 34: ...pling of all 4 channels Under such configurations the data numeration frequency per ADC channel will make 10 1 given ADC conversion frequency Common case fig 5 3for applying all possible synchronizati...

Страница 35: ...re being fulfilled In condition default the record will be stopped until condition on level will be fulfilled again or until software stopping command will be sent Thereby signal areas being selected...

Страница 36: ...synchronization of start on signal edge rev ADC frequency period Duration of inter frame delay Frame size Record interrupting at frame edge until further fulfillment of condition on level or software...

Страница 37: ...is activated when no overloading that data are transmitted unchanged when overloading the data are transmitted with inverted 14 th data bit s sXXXXXXXXXXXXX Based on radix complement representation o...

Страница 38: ...to thrown data volume multiple always of frame size So in E20 10 of revision FIFO buffer overflow will always leads to unavoidable in this case data flow break but unlike revision you may not restart...

Страница 39: ...u apply calibration of ADC data at upper level og library function the abovementioned principle to select overflow alarm is not changed the only difference being linear data calibration function is ap...

Страница 40: ...or damage caused by electrically improper signal connecting For more details on way of signal connection to the measuring system and noise suppression refer to specialized article titled Solutions of...

Страница 41: ...pe Channel matching is shown in fig 6 1 The same matching is graphically shown on E20 10 body Actually in case of accurate handling of E20 10it is not prohibited but not recommended to use domestic co...

Страница 42: ...on 1 ADC channel AGND input Single phase with common land 1 ADC channel input connector screen is connected with AGND 2 ADC channel AGND input Single phase with common land 2 ADC channel input connect...

Страница 43: ...ng body of cable connector DB 37M shall not be connected with any circuit External power connector type DJK 02A cable part relevant to it DJK 10A 1 20 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21...

Страница 44: ...p resistor is not available START GND Input output Input output of data acquisition start signal START and DI16 lines are combined Pull up resistor of 4 7 kOhm to circuit of 5 V 9 27 V GND Input Volta...

Страница 45: ...nal line characteristics Table 6 3 Characteristics of signal lines inputs and outputs operating mode Signal Typ e Input resistance Maximum permissible conditions at input Maximum permissible condition...

Страница 46: ...puts and outputs off mode Signal Type Input resistance Maximum permissible voltage at input Maximum permissible conditions at output ADC channel inputs AI min 1 kOhm 10 V DAC channel outputs AO DI1 DI...

Страница 47: ...output current AGND GND 0 1 AGND GND 0 1 GND GND 0 7 6 4 4 External power supply input characteristic When E20 10 is energized not from AD adapter including in delivery package p 3 3 1 and from exter...

Страница 48: ...output characteristics Table 6 7 External power supply outputs characteristic External circuit power supply source 12V 5V Maximum output current 2 x 35 mA 35 mA 100 mA for E20 10 of revision B 01 Curr...

Страница 49: ...ter different controllers in this case there should be no bandwidth capacity problems otherwise internal USB hub on mother card will not provide 20 MB s for each port If required you can use additiona...

Страница 50: ...om individual power sources then these PC or USB hubs shall have common ground if ground circuit is provided and modules GND circuits shall be interconnected When interconnecting of bidirectional line...

Страница 51: ...ng E20 10 to external circuits you should remember that the most proper connecting of E20 10 is that connecting which would not result in through currents passage via circuits GND AGND GND computer ca...

Страница 52: ...te one the other hand places restrictions on signal internal resistance on direct current because intrinsic input current value multiplied by internal resistance of signal source via direct current wi...

Страница 53: ...he gauge transfer impedance about 9 MOhm serves as divider upper arm So to provide dividing function 1 10 if oscillograph gauge it is required to have connecting in parallel to input E20 10 of resisto...

Страница 54: ...problem if the through currents are detected The following technical ways of solution will help you Ground the connected devices electrically close shorten connecting wires Use galvanic isolation aux...

Страница 55: ...d non optimal is a sequential traversal topology The compromise between the first and the second variant is appropriate in practice Short twisted pairs can be replaced with short screened wire bridles...

Страница 56: ...ge maximum permissible reduced fundamental error of measurement 0 25 Limits of the permissible relative basic error of measuring the AC voltage According to p 7 1 1 7 1 2 Limits of the permissible rel...

Страница 57: ...k MHz where k 3 4 5 30 ADC analog input DC input resistance Minimum 5 MOhm for E20 10 of revision 10 0 5 MOhm forE20 10 of revision Intrinsic input current of analog input for E20 10 of revision 15 0...

Страница 58: ...0 1 E20 10 1 I E20 10 D 1 I limits of the permissible relative basic error of measuring the ac voltage Frequency range of input signal kHz Limits of the permissible relative basic error of measuring t...

Страница 59: ...20 10 SYNC signals START signals 8 ns one period of ADC start frequency START external signal duration min 50 ns 7 2 DAC Parameter characteristics Value Number of channels 2 Bit depth 12 bits Settling...

Страница 60: ...ve function Output current Digital line operational output current Total load output current relatively to connected GND circuit outputs being in logical item state Max 8 mA limiting current see p 6 4...

Страница 61: ...20 10 No Input in phase interference filter Yes Stability under power voltage negative polarity erroneous connection mode 22 Provided External devices power output 5V parameters output voltage output...

Страница 62: ...cted parts 142 132 40 mm Weight Max 0 3 kg Connector type Digital I O DB 37F Connector type USB DUSB BRA42 T11 Analog output connector type Analog input connector types MDNR 9J BN female chassis jack...

Страница 63: ...tter index I correspond to GOST 22261 group 3 with an extended range of operating temperatures environment temperature from 5 to 55 relative humidity at an ambient temperature of 25 C up to 90 air pre...

Страница 64: ...nd common wire of detected device relatively to computer housing or to isolate this device galvanically bu some means See recommendations in Ch 6 In signal spectrum digitalized by E20 10 the component...

Страница 65: ...your situation are required Your name and contact data E20 10 serial number see on the module body or relevant program accessible information What computer which chipset is used and what type of opera...

Страница 66: ...of ADC in real practice M M L Card 2010 5 Terminology is a periodically updated L Card website section 6 FAQ frequency asked questions is a periodically updated L Card website section 7 National Semi...

Страница 67: ...haracteristics of signal lines inputs and outputs off mode 46 Table6 5 Maximum permissible through currents 47 Table 6 6 External power supply input characteristics 47 Table 6 7 External power supply...

Отзывы:

Нет отзывов

Бренды по названию

Популярные бренды

Загрузить еще бренды