5.
Overview of the hardware components
and operation principles
Firstly, the description of hardware components which provides insight into
E20-10
operation principles is given in this chapter and detailing of operational characteristics is given
below. Description does not cover low-level definition of hardware but it is quite sufficient for
understanding of product important performance characteristics.
5.1. Block diagram
Module
E20-10
contains process nodes shown on diagram (
). Consider next
functional unit
E20-10
according to this diagram.
Four identical analog paths
consist of input offset current control circuit, input static
commutator, controlled amplifier, active LPF of 3-order.
Input offset current control circuit
is available in revision В of module
E20-10
only. In
revision A typical input offset current makes -7 µA (in particular, this current caused overswing to
ADC scale negative values under quiescent ADC analog input). This current was amplifier
component property applied in revision A. Amplifier with incomparably lower input current may be
applied in revision B. But, due to the fact of input current existence of revision A could be used in
different propositions (for example, as signal external source connecting sign), that in revision B the
negative offset current can be live on command (therewith, offset current is generated artificially) to
be compatible with old revision, but
input offset current is dead by default in revision B
(p.
).
Input static commutator is designed to
engage mode for measuring module
E20-10
own zero
independently per ADC channel. Measuring of own zero prior data acquisition session and
program record-keeping of measured value may compensate long-term temperature and time ADC
zero drift. It should be noted, that this commutator is unappropriated for such zero compensation
"on-fly" (i.e., during data acquisition).
Controlled amplifier has
3 transfer ratios programmed individually for each ADC channel.
These transfer ratios implement input ADC subranges: ±3 V, ±1 В, ±0.3 V.
Active
LPF in basic version has boundary frequency of 1.25 MHz (optimal for 4-channel
mode at maximum acquisition frequency), and another versions
of
E20-10
with other boundary
frequencies are technically possible (p.
).
Signal from active LPF outputs of each channel enters to
dynamic commutator performing
switching of signals with ADC conversion frequency from four analog paths to ADC input.
Channel numbers switching sequence is arbitrarily given in control list.
Pipelined ADC
— 14-bit high-frequency ADC of LTC2245 type of Linear Technology. This
ADC has two major features which have a direct effect on
E20-10
architecture: deeply pipelined
architecture of this ADC, ADC conversion frequency range of from 1.0 to 10 MHz.
Data enters to FPGA from ADC output. In revision А
E20-10
, beside the above mentioned
mixing of ADC word size overloading feature the data flow is not further converted because
calibration procedure is implemented here by upper-level tools (in computer). To calibrate flow of
10 megasamples per second (20 MB/s) "on-the-fly", especially if more than one module
E20-10is
connected to the computer,
– is a resource-intensive procedure even for modern computer, so,
in
revision B of module E20-10
the data calibration procedure is implemented by FPGA tools
.
9
this issue are to be arranged with L-CARD
