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cPCI-MXS64GX Technical Reference Manual
3.4
3.1.5. Multimedia, History status
CPLD
Address
D7
D6
D5
D4
D3
D2
D1
D0
READ
n92h*
NU
NU
NU
NU
NU
WD_LOCK
NU
CLRHIS
WRITE
n92h*
NU
NU
NU
NU
NU
WD_LOCK
NU
CLRHIS
Power-up Default
1
1
CLRHIS
: When low, clear all history bits. Put this bit to 1 to enable history logging.
WD_LOCK
: When high, lock the state of the enable bit for the digital watchdog
3.1.6. Monitoring status and I/O access
CPLD
Address
D7
D6
D5
D4
D3
D2
D1
D0
READ
n93h*
NU
NU
NU
NU
IDCHIP
NU
I2C_CLK
I2C_DATA
WRITE
n93*h
NU
NU
NU
NU
IDCHIP
NU
I2C_CLK
I2C_DATA
Power-up Default
0
0
0
I2C_DATA
: I2C data
I2C_CLK
: I2C Clock
IDCHIP
: One-wire clock/data for silicon ID chip
3.1.7. Uart 3 PnP configuration
CPLD
Address
D7
D6
D5
D4
D3
D2
D1
D0
READ
n94*h
CND3
CIS3_1
CIS3_0 CBAS3_
1
CBAS3_0 Reserve
d
Reserve
d
Reserve
d
WRITE
n94*h
CND3
CIS3_1
CIS3_0 CBAS3_
1
CBAS3_0 Reserve
d
Reserve
d
Reserve
d
Power-up Default
0
0
0
0
1
0
0
1
CND3
: When low, decode the base address.
CIS3_[1..0]
: COM port interrupt select.
CBAS3_[1..0]
: COM base address select.
Содержание cPCI-MXS64GX
Страница 70: ...cPCI MXS64GX Technical Reference Manual 3 26 1 Rev...
Страница 82: ...4 SOFTWARE SETUPS 1 BIOS SETUP PROGRAM 2 VT100 MODE 4 PART...
Страница 108: ...D 1 D BOARD DIAGRAMS D 1 TOP DEVICES SURFACE MOUNT...
Страница 109: ...cPCI MXS64GX Technical Reference Manual D 2 D 2 ASSEMBLY BOTTOM DIAGRAM...
Страница 110: ...Board Specifications D 3 D 3 MOUNTING HOLES...