28
•
The silk screened DIMM slot identifiers on the board provide information about the
channel and the processor to which they belong.
For example, DIMM_A1 is the first slot on Channel A on processor 1; DIMM_D1 is the
first DIMM socket on Channel D on processor 2.
•
The memory slots associated with a given processor are unavailable if the given
processor socket is not populated.
•
A processor can be installed without populating the associated memory slots,
provided the other processor is installed with associated memory. In this case, the
memory is shared by the processors. However, the platform suffers performance
degradation and latency because of the remote memory accesses.
•
Processor sockets are self-contained and autonomous. However, all memory subsystem
support (i.e., Memory RAS, Error Management, etc.) in the BIOS setup are applied
commonly across processor sockets.
Memory RAS
The server board supports the following memory RAS features:
•
Channel Independent Mode
•
Channel Mirroring Mode
The memory RAS offered by the Intel® Xeon® Processor 5600 Series is done at the
channel level, i.e., during mirroring, channel B mirrors channel A. All DIMM matching
requirements are on a slot- to-slot basis on adjacent channels. For example, to enable
mirroring, corresponding slots on channel A and channel B must have DIMMS of identical
parameters. But DIMMs on adjacent slots on the same channel do not need identical
parameters.
If one socket fails the population requirements for RAS, the BIOS sets all six
channels to the Channel Independent mode. One exception to this rule is when all DIMM
slots for a socket are empty, for example, when only sockets A1, B1, C1 are populated,
mirroring is possible on the platform.
The memory slots of DDR3 channels from the Intel
®
Xeon
®
Processor 5600 Series should be
populated in a “farthest first” fashion. This holds true even in the Channel
Independent mode. This means, for example, that A2 cannot be populated/used if A1 is
empty.
Channel Independent Mode
In Channel Independent mode, multiple channels can be populated in any order (e.g.,
channels B and C can be populated while channel A is empty). Also, DIMMs on adjacent
channels need not have identical parameters. Therefore, all DIMMs are enabled and used
in the Channel Independent mode.
Adjacent slots on a DDR3 channel for the Intel
®
Xeon
®
Processor 5600 Series do not need
matching size and organization. However, the speed of the channel is configured to the
maximum common speed of the DIMMs.
Single channel mode is established by using the Channel Independent mode and
populating DIMM slots from channel A only.
Channel Mirroring Mode
The Intel
®
Xeon
®
Processor 5600 Series supports channel mirroring to configure
available channels of DDR3 DIMMS in a mirrored configuration. Unlike channel sparing,
the mirrored configuration is a redundant image of the memory, and can continue to
operate despite the presence of sporadic uncorrectable errors.
Channel mirroring is a RAS feature in which two identical images of memory data are
maintained, thus providing maximum redundancy. On Intel
®
Xeon
®
Processor 5600 Series
based server boards, mirroring is achieved across channels. Active channels hold the
primary image and the other channels hold the secondary image of the system memory.
