NX-200
15
5-3. PLL IC (IC3)
The PLL IC compares the differences in phases of the
VCO oscillation frequency and the VCTCXO reference
frequency, returns the difference to the VCO CV terminal
and realizes the “Phase Locked Loop” for the return con-
trol. This allows the VCO oscillation frequency to accurately
match (lock) the desired frequency.
When the frequency is controlled by the PLL, the fre-
quency convergence time increases as the frequency differ-
ence increases when the set frequency is changed. To sup-
plement this, the ASIC is used before control by the PLL IC
to bring the VCO oscillation frequency close to the desired
frequency. As a result, the VCO CV voltage does not change
and is always stable at approximately 2.5V.
The desired frequency is set for the PLL IC by the ASIC
(IC108) through the 3-line “SDO1”, “SCK1”, “/PCS_RF”
serial bus. Whether the PLL IC is locked or not is monitored
by the ASIC through the “PLD” signal line. If the VCO is not
the desired frequency (unlock), the “PLD” logic is low.
5-4. Doubler (Q4)
The doubler (Q4) extracts the twice harmonic component
from the signal from the VCO. This twice harmonic compo-
nents is then fed into PLL (IC3) through band pass fi lter.
Band pass fi lter is consists of two fi lter. One is for TX
(L3,L5,L7) and pass band is 272.0 to 348.0MHz. The other
is for RX 1st local (L2,L6,L30) and pass band is 388.1 to
464.1MHz.
5-5. Local Switch (D100, D201)
The connection destination of the signal output from the
buffer amplifier (Q100) is changed with the diode switch
(D100) that is controlled by the transmission power supply,
50T, and the diode switch (D201) that is controlled by the
receive power supply, 50R. If the 50T logic is high, it is con-
nected to a send-side pre-drive (Q102). If the 50T logic is
low, it is connected to a receive-side mixer (Q203).
6. Control Circuit
The control circuit consists of the ASIC (IC108) and its
peripheral circuits. IC108 mainly performs the following;
1) Switching between transmission and reception by PTT
signal input.
2) Reading system, zone, frequency, and program data
from the memory circuit.
3) Sending frequency program data to the PLL.
4) Controlling squelch on/off by the DC voltage from the
squelch circuit.
5) Controlling the audio mute circuit by decode data input.
6-1. ASIC
The ASIC (IC108) is a 32-bit RISC processor, equipped
with peripheral function and ADC/DAC.
This ASIC operates at 18.432MHz clock and 3.3V /1.5V
DC. It controls the fl ash memory, SRAM, DSP, the receive
circuit, the transmitter circuit, the control circuit, and the dis-
play circuit and transfers data to or from an external device.
Fig. 7 PLL block diagram
CIRCUIT DESCRIPTION
Loop
Filter
BUFF
AMP
Ripple
Filter
VCO
150C
VC
TCXO
PLL
IC
IC3
Q11
Q8,Q10
D8,D9,D12~D17
BUFF
AMP
Q100
Q4
SDO1
SCK1
/PCS_RF
X1
19.2MHz
T/R
SW
D100,D201
50C
50C
to TX stage
50T 50R
to 1st Mixer
IC4 (1/2)
Q12
Q3
IC2
CV
VCO_MOD
ASSIST
BPF(RX)
L2,L6,L30
BPF(TX)
L3,L5,L7
RF
SW
D5,D6
RF
SW
D2,D3
Doubler
