vi
Analog Input Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . C-11
Data Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-13
A/D Conversion Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-15
A/D Data Lost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-15
Analog Output Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . C-15
Analog Output Initialization . . . . . . . . . . . . . . . . . . . . . . . . C-17
Internal Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-17
Synchronous Analog Input/Output Clocking . . . . . . . . . . . C-17
External Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-18
External Triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-18
Data Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-19
D/A Conversion Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-20
D/A Data Lost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-21
Digital Input and Output Subsystems . . . . . . . . . . . . . . . . . . . C-21
Logical Channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-21
Digital Input Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . C-22
Digital Output Initialization . . . . . . . . . . . . . . . . . . . . . . . . C-22
Digital I/O Conversion Delay . . . . . . . . . . . . . . . . . . . . . . . C-22
Digital I/O Data Lost. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-23
Counter/Timer Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-23
Counter/Timer Initialization . . . . . . . . . . . . . . . . . . . . . . . . C-23
Counter/Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . C-23
Index
List of Figures
Figure 2-1.
Block Diagram of DAS-1800HC Series Board . . . 2-2
Figure 2-2.
Timing of Conversion Modes
for a Queue of Channels 4 to 7 . . . . . . . . . . . . . . 2-10
Figure 2-3.
Enabling Conversions with Software
Triggering/Gating and With Internal
and External Clock Sources. . . . . . . . . . . . . . . . . 2-13
Figure 2-4.
Enabling Conversions with a Hardware Trigger . 2-14
Figure 2-5.
Hardware Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Figure 2-6.
Timing Relationship between Data
from DO0 to DO7 and Latch Strobe DOSTB . . . 2-19
Figure 2-7.
Timing for the Generation of TGOUT . . . . . . . . 2-20
Figure 2-8.
Timing for SSHO Generation
When Not Used for SSH Hardware. . . . . . . . . . . 2-21
Figure 3-1.
Location of Base Address Switch . . . . . . . . . . . . . 3-5
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