̶
25
̶
SW-4000M-PMCL
[Binning On]
Tap
Geometry
Bit/
Pixel
CL Pixel
Clock
[MHz]
Delay time
From Trigger
to EEN
falling [A]
(usec)
Period
From EEN
Falling to
LVAL rising
[B](usec)
EEN
invalid time
[C](usec)
Data
invalid time
[D](CLK)
Data valid
time [F]
(CLK)
Line Period
[G](CLK)
1X2
8/10
31.70
7.8
13.9
7.8
10
2048
2058
42.41
7.8
13.8
7.8
17
2048
2065
63.39
7.8
13.7
7.8
10
2048
2058
84.82
7.8
13.7
7.8
18
2048
2066
1X3
8
31.70
7.8
13.9
7.8
7
1364
1371
42.41
7.8
13.8
7.8
12
1364
1376
63.39
7.8
13.7
7.8
8
1364
1372
84.82
7.8
13.7
7.8
183
1364
1547
1X4
8/10
31.70
7.8
13.9
7.8
5
1024
1029
42.41
7.8
13.8
7.8
9
1024
1033
63.39
7.8
13.7
7.8
132
1024
1156
84.82
7.8
13.7
7.8
523
1024
1547
1X8
8/10
31.70
7.8
13.9
7.8
66
512
578
42.41
7.8
13.8
7.8
262
512
774
63.39
7.8
13.7
7.8
644
512
1156
84.82
7.8
13.7
7.8
1035
512
1547
1X10
8
31.70
7.8
13.9
7.8
169
409
578
42.41
7.8
13.8
7.8
365
409
774
63.39
7.8
13.7
7.8
747
409
1156
84.82
7.8
13.7
7.8
1138
409
1547