REL1.1
Page 7 of 89
iWave Systems Technologies Pvt. Ltd.
Zynq-Ult MPSoC SOM Development Platform Hardware User Guide
List of Tables
Table 1: Acronyms & Abbreviations............................................................................................................................. 8
Table 2: Terminology ................................................................................................................................................ 10
Table 3: PS-GTR Lane Selection Switch Setting .......................................................................................................... 17
Table 4: PCIe x4 Connector Pin Assignment ............................................................................................................... 19
Table 5: Display Port Connector Pin Assignment........................................................................................................ 22
Table 6: USB Type-C Pin Assignment ......................................................................................................................... 25
Table 7: M.2 SATA Connector Pin Assignment ........................................................................................................... 27
Table 8: CAN0 Header Pin Assignment ...................................................................................................................... 33
Table 9: SFP+ Connector Pin Assignment ................................................................................................................... 37
Table 10: FMC HPC Connector1 Pin Assignment ........................................................................................................ 42
Table 11: FMC HPC Connector2 Pin Assignment ........................................................................................................ 57
Table 12: Pmod Connector1 Pin Assignment ............................................................................................................. 70
Table 13: Pmod Connector2 Pin Assignment ............................................................................................................. 70
Table 14: Clock Synthesizer Output Clocks ................................................................................................................ 71
Table 15: IO Expander pinout details ......................................................................................................................... 73
Table 16: JTAG Header Pin Assignment ..................................................................................................................... 75
Table 17: GPIO Header Pin Assignment ..................................................................................................................... 76
Table 18: Power Input Requirement .......................................................................................................................... 82
Table 19: Power Output Specification ....................................................................................................................... 83
Table 20: Environmental Specification....................................................................................................................... 84
Table 21: Orderable Product Part Numbers ............................................................................................................... 88