REL1.1
Page 17 of 89
iWave Systems Technologies Pvt. Ltd.
Zynq-Ult MPSoC SOM Development Platform Hardware User Guide
The PS-GTR Lane selection switch (SW5) setting and corresponding interface selection option is explained below.
Table 3: PS-GTR Lane Selection Switch Setting
PS-GTR Lanes
PS-GTR Lane Selection Switch (SW5)
Switch Bit
Number
Switch Bit Position
ON
OFF
Lane0
Bit1
PS-GTR Lane0 is connected to Lane0
of PCIe x4 connector (default)
PS-GTR Lane0 is connected to Lane1
of DP connector
Lane1
Bit2
PS-GTR Lane1 is connected to Lane1
of PCIe x4 connector
PS-GTR Lane1 is connected to Lane0
of DP connector (default)
Lane2
Bit3
PS-GTR Lane2 is connected to Lane2
of PCIe x4 connector
PS-GTR Lane2 is connected to Lane1
of USB3.0 TypeC connector (default)
Lane3
Bit4
PS-GTR Lane3 is connected to Lane3
of PCIe x4 connector
PS-GTR Lane3 is connected to M.2
SATA connector (default)
Figure 5: PS-GTR Lane Selection Switch