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i.MX8 SMARC SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
2.7.10 Audio Interface
The i.MX8 SMARC SOM supports I2S0 and I2S1 channels of SMARC Edge connector from CPU’s SAI0 and SAI1 channels
respectively. The SAI peripheral provides a synchronous audio interface that supports full duplex serial interfaces with
frame synchronization such as I2S, AC97 and other audio CODEC/DSP interfaces. The SAI general features are including
Transmitter section with independent bit clock and frame sync, Maximum frame size of 32 words, Word size from 8-
bits to 32-bits and Supports graceful restart after FIFO error. Only Transmitter Clock and Transmitter Left-Right Clock
(LRCK) is supported as per SMARC specification.
In i.MX8 SMARC SOM the transmitter is configured for asynchronous mode and the receiver is configured for
synchronous mode, hence both transmitter and receiver will use the transmitter bit clock and frame sync.
For more details on SMARC Edge SD pinouts on SMARC Edge connector, refer below table:
SMARC
Pin No. SMARC Edge
Signal Name
CPU Ball Name/
Pin Number
Signal Type/
Termination
Description
S38 MCLK_OUT0 MCLK_OUT0/
BD4 O, 1.8V CMOS Master Clock for Audio codec
S39 SAI1_TXFS SAI1_TXFS/
AV2 O, 1.8V CMOS Serial Audio Interface Channel1 Frame Sync
/Left Right Clock
S40 SAI1_TXD SAI1_TXD/
AU1 O, 1.8V CMOS Serial Audio Interface Channel1 Data Output
S41 SAI1_RXD SAI1_RXD/
AV4 I, 1.8V CMOS Serial Audio Interface Channel1 Data Input
S42 SAI1_TXC SAI1_TXC/
AU5 O, 1.8V CMOS/
33E Series Serial Audio Interface Channel1 Clock
S50 AUD_SAI0_TXFS SPI2_CS1/
AY2 O, 1.8V CMOS Serial Audio Interface Channel0 Left Right
Clock
S51 AUD_SAI0_TXD SPI0_SDO /
AY6 O, 1.8V CMOS Serial Audio Interface Channel0 Data
Output
S52 AUD_SAI0_RXD SPI0_SDI /BA5 I, 1.8V CMOS Serial Audio Interface Channel0 Data Input
S53 AUD_SAI0_TXC SPI0_CS1 /
BA3 O, 1.8V CMOS/
33E Series Serial Audio Interface Channel0 Clock
2.7.11 SPI Interface
The i.MX8 CPU supports low power Serial Peripheral Interface (SPI) module that supports an efficient interface to an
SPI bus as a master and/or a slave with maximum clock speed of 40MHz. The i.MX8 SMARC SOM supports SPI0
channels of the SMARC Edge connector with SPI3 of CPU side.
For more details on SPI pinouts, refer below table:
SMARC
Pin No.
SMARC Edge
Signal Name
CPU Ball Name/
Pin Number
Signal Type/
Termination
Description
P43 SPI3_CS0 SPI3_CS0/BG5 O, 1.8V CMOS SPI0 Chip Select 0
P44 SPI3_SCLK SPI3_SCLK/BF6 O, 1.8V CMOS/
33E Series SPI0 Clock
P45 SPI3_MISO SPI3_MISO/BE5 I, 1.8V CMOS SPI0 Master IN Slave Out