REL1.0
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i.MX8 SMARC SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
SMARC
Pin No.
SMARC Edge
Signal Name
CPU Ball Name/
Pin Number
Signal Type/
Termination
Description
S88
PCIE1_B_RX0_N
PCIE1_RX0_N/
B22
I, PCIe
PCIe Channel-B Receiver Negative.
S90
PCIE1_B_TX0_P
PCIE1_TX0_P/
B24
O, PCIe /
0.22uF AC Couple
PCIe Channel-B Transmitter Positive.
S91
PCIE1_B_TX0_N
PCIE1_TX0_N/
C25
O, PCIe /
0.22uF AC Couple
PCIe Channel-B Transmitter Negative.
2.7.6
SATA Interface
The i.MX8 CPU supports SATA-3(Gen3: 6GHz to get 6GHz baud clock). This is in addition to the standard PCIe 3.0 and
connected to SMARC SATA Edge connector pins via 0.022uF AC coupled capacitors on both TX an RX lines.
For more details on SATA pinouts, refer below table:
SMARC
Pin No.
SMARC Edge
Signal Name
CPU Ball Name/
Pin Number
Signal Type/
Termination
Description
P48
PCIE_SATA0_TX0_P
PCIE_SATA0_
TX0_P/ B16
O, SATA /
0.022uF AC Couple
SATA Transmit Lane Positive
P49
PCIE_SATA0_TX0_N
PCIE_SATA0_
TX0_N/ C17
O, SATA /
0.022uF AC Couple
SATA Transmit Lane Negative
P51
PCIE_SATA0_RX0_P
PCIE_SATA0_
RX0_P/ A19
I, SATA /
0.022uF AC Couple
SATA Receive Lane Positive
P52
PCIE_SATA0_RX0_N
PCIE_SATA0_
RX0_N/ B20
I, SATA /
0.022uF AC Couple
SATA Receive Lane Negative
S54
SATA_ACT#
(GPIO1_18)
MIPI_DSI0_
GPIO0_00/BD30
O, 3.3V CMOS
GPIO used as SATA Activity indication
2.7.7
MIPI CSI Camera
The i.MX8 CPU supports two 4-lane camera interfaces, the CSI-2 Rx Controller Core implements all three layers defined
by the CSI-2 Specification: Pixel to Byte Packing, Low Level Protocol, and Lane Management. The D-PHY interface of
the CSI-2 Rx Controller Core supports PHY Protocol Interface (PPI) compatible MIPI D-PHYs. The Local Interface is an
easy to use pixel-based interface that supports 1 to 4 virtual channels and all data types. The Local interface runs at
the User Interface clock rate for all implementations. The CSI-2 Rx Controller Core takes care of all packet formatting
details and transmission over the MIPI bus. The i.MX8 SMARC SOM supports one two lane and one four lane MIPI CSI
camera interface via SMARC Edge connector along with the other controlling signals. Here all CSI1 lane [3:0] are
connected to SMARC edge connector, but only CSI0 lane [1:0] are connected to SMARC edge connector whereas CSI0
lane [3:2] are connected to expansion connector.
For more details on MIPI CSI0 SMARC pinouts, refer below table:
SMARC
Pin No.
SMARC Edge
Signal Name
CPU Ball Name/
Pin Number
Signal Type/
Termination
Description
S5
MIPI_CSI0_I2C0_SCL
MIPI_CSI0_I2C0
_SCL/
BH24
O, 1.8V CMOS/
2.2K PU
MIPI CSI0 I2C Clock.
