Intergraph TD-x10 Setup, Справочное руководство системы

Страница: 68 / 98

58
Address Device
03E8 - 03EF Serial Port COM3
03F0 - 03F7 I/O Controller
03F8 - 03FF Serial Port COM1
Memory Address Map
The following table lists the memory address map assignments.
Memory Address Size Assignment
00000000 - 0009FFFF 640K System board memory
000A0000 - 000BFFFF 128K Video memory
000C0000 - 000C7FFF 32K Video ROM
000C8000 - 000DFFFF 96K Available I/O Adapter ROM
000E0000 - 000EFFFF 64K BIOS ROM and PCMCIA
000F0000 - 000FFFFF 64K BIOS ROM
00100000 - 0FFFFFFF 256M Expansion memory
10000000 - 3FFFFFFF ----- Reserved
PCI to ISA Bus Interrupt Mapping
The ISA bridge (Intel 82379AB) provides the sixteen conventional ISA interrupts, plus four interrupt
request pins for PCI peripheral interrupts (PIRQ0 through PIRQ3). For PC-AT architecture
compatibility reasons, the PCI interrupts are routed to the ISA interrupts within the ISA bridge. The
assertion of a PCI interrupt concludes in an ISA interrupt being asserted.
The 8-bit PIRQ Route Control Registers in the ISA bridge determine to which ISA interrupt a PIRQ is
routed. Four PIRQ Route Control Registers are used for the PCI interrupts, located at the ISA bridge
address offsets defined below.
PCI Interrupt Request Address Offset (Hex)
PIRQ0 60
PIRQ1 61
PIRQ2 62
PIRQ3 63
Bit 7 of each PIRQ registers enable (Low) or disable (High) the routing of the PIRQ to an ISA
interrupt. The lowest four bits (3:0) of each PIRQ register determines to which ISA interrupt the PIRQ
will be routed, as defined below.
Bits (3:0) of PIRQ ISA Interrupt Bits (3:0) of PIRQ ISA Interrupt
0000 Reserved 1000 Reserved
0001 Reserved 1001 IRQ9
0010 Reserved 1010 IRQ10
0011 IRQ3 1011 IRQ11
0100 IRQ4 1100 IRQ12
0101 IRQ5 1101 Reserved