Intergraph DHAF02430, Справочное руководство системы

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PCI to ISA Bus Interrupt Mapping
The ISA bridge (Intel 82379AB) or MSMT359 the sixteen conventional ISA interrupts, plus four
interrupt request pins for PCI peripheral interrupts (PIRQ0 through PIRQ3). For PC-AT architecture
compatibility reasons, the PCI interrupts are routed to the ISA interrupts within the ISA bridge. The
assertion of a PCI interrupt concludes in an ISA interrupt being asserted.
The 8-bit PIRQ Route Control Registers in the ISA bridge determine to which ISA interrupt a PIRQ
or MSMT359 is routed. Four PIRQ Route Control Registers are used for the PCI interrupts, located
at the ISA bridge address offsets defined below.
PCI Interrupt Request Address Offset (Hex)
PIRQ0 60
PIRQ1 61
PIRQ2 62
PIRQ3 63
Bit 7 of each PIRQ registers enable (Low) or disable (High) the routing of the PIRQ to an ISA
interrupt. The lowest four bits (3:0) of each PIRQ register determines to which ISA interrupt the
PIRQ will be routed, as defined below.
Bits (3:0) of PIRQ ISA Interrupt Bits (3:0) of PIRQ ISA Interrupt
0000 Reserved 1000 Reserved
0001 Reserved 1001 IRQ9
0010 Reserved 1010 IRQ10
0011 IRQ3 1011 IRQ11
0100 IRQ4 1100 IRQ12
0101 IRQ5 1101 Reserved
0110 IRQ6 1110 IRQ14
0111 IRQ7 1111 IRQ15
PCI Bus Configuration Space
The table below lists the configuration space used for the primary PCI bus. The PCI bus uses type 1
configuration access, which specifies two 32-bit I/O ports used as the index register (0CF8h) and the
data register (0CFCh).
Device Device Number 0CF8h Value
Host-to-PCI Bridge (PCMC) 0 800000XX
PCI-to-ISA Bridge 2 800010XX
Graphics Accelerator 5 800028XX
Ethernet Controller 6 800030XX
SCSI Controller 7 800038XX
PCI Slot 1 D 800068XX
PCI Slot 2 E 800070XX
PCI Slot 3 F 800078XX