Intel SR6850HW4 - Server Platform - 0 MB RAM, Руководство по эксплуатации продукта

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242 Intel® Server Platforms SR6850HW4 and SR6850HW4/M Product Guide
Name Location Default Stuffed Jumper State
(Default in Bold)
BMC RESET J8C2 Stuff
Empty
1 – 2 = BMC enabled
2 – 3 = BMC Disabled
FWHID J8C3 Stuff
Empty
1-2 = Enables BMC controls FWHID swap
2-3 = Force FWHID swap
Figure 127. Main Board Jumper Locations
I
2
C POST Code Headers
The main board has a 5-pin header (with the fourth pin removed) for the I
2
C POST-code card. The
headers are J3A1 on the I/O riser card and J6C1 on the memory board. The I
2
C signals are from the
SMB bus in the Intel
®
82801EB I/O Controller Hub 5. The data and clock signals are pulled up to
3.3 V standby. Table 20 shows the pin assignments.
Table 20. J3A1 and J6C1 I
2
C POST Code Headers
Pin Signal
1 12 V Standby
2 SMBDATA
3 SMBCLK
4 NC – pin removed
5 Ground