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Intel® Server Board SE7520AF2 TPS
Functional Architecture
Revision 1.2
81
Intel order number C77866-003
determine which host bus agents they are, Agent 0 or Agent 6, according whether their
BREQ0_L or BREQ1_L is asserted. This determines bus arbitration priority and order.
The processor(s) in the system determines which processor will be the BSP by using Bootstrap
Inter Processor Interrupts (BIPI) on the APIC data bus. The non-BSP processor becomes an
application processor and idles, waiting for a Startup Inter Processor Interrupt (SIPI). The BSP
begins by fetching the first instruction from the reset vector FFFFFFF0h. The Intel® E7520
chipset registers are updated to reflect memory configuration, all SDRAM is sized and
initialized. All PCI and ISA I/O subsystems are initialized and prepared for booting.
3.6 Clock Generation and Distribution
The main clock source is the CK409B synthesizer/driver component. This device generates
majority of the clocks in the design, including the serial reference clock source provided to the
DB800 differential buffer. Individual serial reference clocks required for PCI Express*
devices/slots are then generated by the DB800. All buses on the Intel® Server Board
SE7520AF2 operate using synchronous clocks. Clock synthesizer/driver circuitry on the
baseboard generates clock frequencies and voltage levels as detailed in the following table.
Table 29. Clock Generation and Distribution
Clk Pin
Device
REF1 ICH5R
14MHz
REF0 Video
PCIF0 ICH5R
PCIF1 SIO3
PCIF2 IMM
33MHz
PCI0
Video – ATI Rage XL
USB_48 ICH5R
48MHz
DOT_48 SIO3
3V66_0 MCH
66MHz
3V66_1 ICH5R
SRC_P DB800
100 MHz
SRC_N DB800
CPU0 MCH
CPU0_N MCH
CPU1 CPU2
CPU1_N CPU2
CPU2 CPU1
CPU2_N CPU1
CPU3 XDP
CK409B
166MHz
CPU3_N XDP
Clk Pin
Device
DIF_0_P ICH5R
DIF_0_N ICH5R
DIF_1_P MCH
DB800
100MHz
DIF_1_N MCH