Intel® Server System R2000WF Product Family Technical Product Specification
126
B.1.
Early POST Memory Initialization MRC Diagnostic Codes
Memory initialization at the beginning of POST includes multiple functions: discovery, channel training,
validation that the DIMM population is acceptable and functional, initialization of the IMC and other
hardware settings, and initialization of applicable RAS configurations.
The MRC progress codes are displayed to the diagnostic LEDs that show the execution point in the MRC
operational path at each step.
Table 77. MRC progress codes
Checkpoin
t
Diagnostic LED Decoder
Description
Subsequences /
Subfunctions
1 = LED On, 0 = LED Off
Upper Nibble
Lower Nibble
MS
B
LSB
8h
4h 2h 1h 8h 4h 2h
1h
LED #
#7
#6 #5 #4 #3 #2 #1
#0
MRC Progress codes
B0h
1
0
1
1
0
0
0
0
Detect DIMM population
N/A
B1h
1
0
1
1
0
0
0
1
Set DDR4 frequency
N/A
B2h
1
0
1
1
0
0
1
0
Gather remaining SPD data
N/A
B3h
1
0
1
1
0
0
1
1
Program registers on the memory
controller level
N/A
B4h
1
0
1
1
0
1
0
0
Evaluate RAS modes and save rank
information
N/A
B5h
1
0
1
1
0
1
0
1
Program registers on the channel
level
N/A
B6h
1
0
1
1
0
1
1
0
Perform the JEDEC defined
initialization sequence
N/A
B7h
1
0
1
1
0
1
1
1
Train DDR4 ranks
N/A
1h
0
0
0
0
0
0
0
1
Train DDR4 ranks
Read DQ/DQS training
2h
0
0
0
0
0
0
1
0
Train DDR4 ranks
Receive Enable training
3h
0
0
0
0
0
0
1
1
Train DDR4 ranks
Write Leveling training
4h
0
0
0
0
0
1
0
0
Train DDR4 ranks
Write DQ/DQS training
5h
0
0
0
0
0
1
0
1
Train DDR4 ranks
DDR channel training
done
B8h
1
0
1
1
1
0
0
0
Initialize CLTT/OLTT
N/A
B9h
1
0
1
1
1
0
0
1
Hardware memory test and init
N/A
BAh
1
0
1
1
1
0
1
0
Execute software memory init
N/A
BBh
1
0
1
1
1
0
1
1
Program memory map and
interleaving
N/A
BCh
1
0
1
1
1
1
0
0
Program RAS configuration
N/A
BFh
1
0
1
1
1
1
1
1
MRC is done
N/A
