Errata
40
Specification Update
BG66.
PCI Express Graphics x16 Receiver Error Reported When Receiver With L0s
Enabled and Link Retrain Performed
Problem:
If the Processor PCI Express root port is the receiver with L0s enabled and the root port
itself initiates a transition to the recovery state via the retrain link configuration bit in
the 'Link Control' register (Bus 0; Device 1 and 6; Function 0; Offset B0H; bit 5), then
the root port may not mask the receiver or bad DLLP (Data Link Layer Packet) errors as
expected. These correctable errors should only be considered valid during PCIe
configuration and L0 but not L0s. This causes the processor to falsely report correctable
errors in the 'Device Status' register (Bus 0; Device 1 and 6; Function 0; Offset AAH;
bit 0) upon receiving the first FTS (Fast Training Sequence) when exiting Receiver L0s.
Under normal conditions there is no reason for the Root Port to initiate a transition to
Recovery. Note: This issue is only exposed when a recovery event is initiated by the
processor.
Implication: The processor does not comply with the PCI Express 2.0 Specification. This does not
impact functional compatibility or interoperability with other PCIe devices.
Workaround:None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
BG67.
Internal Parity Error May Be Incorrectly Signaled during Deep Power Down
Technology (code name C6 state) Exit
Problem:
In a complex set of internal conditions an internal parity error may occur during a Core
Deep Power Down Technology (code name C6 state) exit.
Implication: Due to this erratum, an uncorrected error may be reported and a machine check
exception may be triggered.
Workaround:It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
BG68.
PMIs during Core Deep Power Down Technology (code name C6 state)
Transitions May Cause the System to Hang
Problem:
If a performance monitoring counter overflows and causes a PMI (Performance
Monitoring Interrupt) at the same time that the core enters Deep Power Down
Technology (code name C6 state), then this may cause the system to hang.
Implication: Due to this erratum, the processor may hang when a PMI coincides with core Deep
Power Down Technology (code name C6 state) entry.
Workaround:It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
BG69.
2-MB Page Split Lock Accesses Combined with Complex Internal Events May
Cause Unpredictable System Behavior
Problem:
A 2-MB Page Split Lock (a locked access that spans two 2-MB large pages) coincident
with additional requests that have particular address relationships in combination with
a timing sensitive sequence of complex internal conditions may cause unpredictable
system behavior.
Implication: This erratum may cause unpredictable system behavior. Intel has not observed this
erratum with any commercially-available software.
