Specification Update
41
Errata
Workaround:None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
BG70.
Extra APIC Timer Interrupt May Occur during a Write to the Divide
Configuration Register
Problem:
If the APIC timer Divide Configuration Register (Offset 03E0H) is written at the same
time that the APIC timer Current Count Register (Offset 0390H) reads 1H, it is possible
that the APIC timer will deliver two interrupts.
Implication: Due to this erratum, two interrupts may unexpectedly be generated by an APIC timer
event.
Workaround:Software should reprogram the Divide Configuration Register only when the APIC timer
interrupt is disarmed.
Status:
For the steppings affected, see the Summary Tables of Changes.
BG71.
8259 Virtual Wire B Mode Interrupt May Be Dropped When It Collides with
Interrupt Acknowledge Cycle from the Preceding Interrupt
Problem:
If an un-serviced 8259 Virtual Wire B Mode (8259 connected to IOAPIC) External
Interrupt is pending in the APIC and a second 8259 Virtual Wire B Mode External
Interrupt arrives, the processor may incorrectly drop the second 8259 Virtual Wire B
Mode External Interrupt request. This occurs when both the new External Interrupt and
Interrupt Acknowledge for the previous External Interrupt arrive at the APIC at the
same time.
Implication: Due to this erratum, any further 8259 Virtual Wire B Mode External Interrupts will
subsequently be ignored.
Workaround:Do not use 8259 Virtual Wire B mode when using the 8259 to deliver interrupts.
Status:
For the steppings affected, see the Summary Tables of Changes.
BG72.
CPUID Incorrectly Reports a C-State as Available When This State Is
Unsupported
Problem:
CPUID incorrectly reports a non-zero value in CPUID MONITOR/MWAIT leaf (5H) EDX
[19:16] when the processor does not support an MWAIT with a target C-state EAX
[7:4] > 3.
Implication: If an MWAIT instruction is executed with a target C-state EAX [7:4] > 3 then
unpredictable system behavior may result.
Workaround:It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
BG73.
The Combination of a Page-Split Lock Access and Data Accesses That Are Split
across Cacheline Boundaries May Lead to Processor Livelock
Problem:
Under certain complex micro-architectural conditions, the simultaneous occurrence of a
page-split lock and several data accesses that are split across cacheline boundaries
may lead to processor livelock.
Implication: Due to this erratum, a livelock may occur that can only be terminated by a processor
reset. Intel has not observed this erratum with any commercially-available software.
