Errata
28
Specification Update
BG29.
Infinite Stream of Interrupts May Occur If an ExtINT Delivery Mode Interrupt
Is Received While All Cores Are in Deep Power Down Technology (code name
C6 state)
Problem:
If all logical processors in a core are in Deep Power Down Technology (code name C6
state), an ExtINT delivery mode interrupt is pending in the xAPIC and interrupts are
blocked with EFLAGS.IF=0, the interrupt will be processed after Deep Power Down
Technology (code name C6 state) wakeup and after interrupts are re-enabled
(EFLAGS.IF=1). However, the pending interrupt event will not be cleared.
Implication: Due to this erratum, an infinite stream of interrupts will occur on the core servicing the
external interrupt. Intel has not observed this erratum with any commercially-available
software/system.
Workaround:None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
BG30.
Two xAPIC Timer Event Interrupts May Unexpectedly Occur
Problem:
If an xAPIC timer event is enabled and while counting down the current count reaches
1 at the same time that the processor thread begins a transition to a low power C-
state, the xAPIC may generate two interrupts instead of the expected one when the
processor returns to C0.
Implication: Due to this erratum, two interrupts may unexpectedly be generated by an xAPIC timer
event.
Workaround:None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
BG31.
EOI Transaction May Not Be Sent If Software Enters Core Deep Power Down
Technology (code name C6 state) during an Interrupt Service Routine
Problem:
If core Deep Power Down Technology (code name C6 state) is entered after the start of
an interrupt service routine but before a write to the APIC EOI register, the core may
not send an EOI transaction (if needed) and further interrupts from the same priority
level or lower may be blocked.
Implication: EOI transactions and interrupts may be blocked when core Deep Power Down
Technology (code name C6 state) is used during interrupt service routines. Intel has
not observed this erratum with any commercially-available software.
Workaround:None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
