Specification Update
39
Errata
BG63.
MSR_TURBO_RATIO_LIMIT MSR May Return Intel® Turbo Boost Technology
Core Ratio Multipliers for Non-Existent Core Configurations
Problem:
MSR_TURBO_RATIO_LIMIT MSR (1ADH) is designed to describe the maximum Intel
Turbo Boost Technology potential of the processor. On some processors, a non-zero
Intel Turbo Boost Technology value will be returned for non-existent core
configurations.
Implication: Due to this erratum, software using the MSR_TURBO_RATIO_LIMIT MSR to report Intel
Turbo Boost Technology processor capabilities may report erroneous results.
Workaround:It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
BG64.
PCI Express x16 Port Logs Bad TLP Correctable Error When Receiving a
Duplicate TLP
Problem:
In the PCI Express 2.0 Specification a receiver should schedule an ACK and discard a
duplicate TLP (Transaction Layer Packet) before ending the transaction within the data
link layer. In the processor, the PCI Express x16 root port will set the Bad TLP status bit
in the Correctable Error Status Register (Bus 0; Device 1 and 6; Function 0; Offset
1D0h; bit 6) in addition to scheduling an ACK and discarding the duplicate TLP. Note:
The duplicate packet can be received only as a result of a correctable error in the other
end point (Transmitter).
Implication: The processor does not comply with the PCI Express 2.0 Specification. This does not
impact functional compatibility or interoperability with other PCIe devices.
Workaround:None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
BG65.
PCI Express x16 Root Port Incorrectly NAK's a Nullified TLP
Problem:
In the processor, the PCI Express root port may NAK a nullified TLP (Transaction Layer
Packet). This behavior is a result of an incorrect DW (Double Word) enable generation
on the processors when packets end with EDB (End Bad Symbol). This also occurs only
if total TLP length <= 8 DW in which CRC (Cyclic Redundancy Check) check/framing
upstream checks will fail. This failure causes a NAK to be unexpectedly generated for
TLP's which have packets with inverted CRC and EDB's. The PCI-e specification revision
2.0 states that such cycles should be dropped and no NAK should be generated. The
processor should NAK a nullified TLP only when there is a CRC error or a sequence
check fail.
Implication: The processor does not comply with the PCI Express 2.0 Specification. This does not
impact functional compatibility or interoperability with other PCIe devices.
Workaround:None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
