Specification Update
35
Errata
BG50.
Pending x87 FPU Exceptions (#MF) May Be Signaled Earlier Than Expected
Problem:
x87 instructions that trigger #MF normally service interrupts before the #MF. Due to
this erratum, if an instruction that triggers #MF is executed while Enhanced Intel
SpeedStep® Technology transitions, Intel® Turbo Boost Technology transitions, or
Thermal Monitor events occur, the pending #MF may be signaled before pending
interrupts are serviced.
Implication: Software may observe #MF being signaled before pending interrupts are serviced.
Workaround:None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
BG51.
Multiple Performance Monitor Interrupts Are Possible on Overflow of
IA32_FIXED_CTR2
Problem:
When multiple performance counters are set to generate interrupts on an overflow and
more than one counter overflows at the same time, only one interrupt should be
generated. However, if one of the counters set to generate an interrupt on overflow is
the IA32_FIXED_CTR2 (MSR 30BH) counter, multiple interrupts may be generated
when the IA32_FIXED_CTR2 overflows at the same time as any of the other
performance counters.
Implication: Multiple counter overflow interrupts may be unexpectedly generated.
Workaround:None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
BG52.
LBRs May Not Be Initialized during Power-On Reset of the Processor
Problem:
If a second reset is initiated during the power-on processor reset cycle, the LBRs (Last
Branch Records) may not be properly initialized.
Implication: Due to this erratum, debug software may not be able to rely on the LBRs out of power-
on reset.
Workaround:Ensure that the processor has completed its power-on reset cycle prior to initiating a
second reset.
Status:
For the steppings affected, see the Summary Tables of Changes.
BG53.
LBR, BTM or BTS Records May Have Incorrect Branch from Information after
an Enhanced Intel SpeedStep® Technology Transition, T-states, C1E, or
Adaptive Thermal Throttling
Problem:
The “From” address associated with the LBR (Last Branch Record), BTM (Branch Trace
Message) or BTS (Branch Trace Store) may be incorrect for the first branch after an
Enhanced Intel SpeedStep Technology transition, T-states, C1E (C1 Enhanced), or
Adaptive Thermal Throttling.
Implication: When the LBRs, BTM or BTS are enabled, some records may have incorrect branch
“From” addresses for the first branch after an Enhanced Intel SpeedStep Technology
transition, T-states, C1E, or Adaptive Thermal Throttling.
Workaround:None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
