Intel PCH-LP, Руководство по программированию

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Intel Confidential
Descriptor Overview
4.1.7.4 VSCCn—Vendor Specific Component Capabilities n
(Flash Descriptor Records)
Memory Address: VTBA + 004h + (n*8)h Size: 32 bits
Note: “n” is an integer denoting the index of the Intel
®
ME VSCC table.
Notes:
1.Bit 3 (WEWS) and/or bit 4 (WSR) should not be set to ‘1’ if there are non volatile bits in the SPI flash’s status
register. This may lead to premature flash wear out.
2.This is not an atomic (uninterrupted) sequence. The PCH will not wait for the status write to complete before
issuing the next command, potentially causing SPI flash instructions to be disregarded by the SPI flash
part. If the SPI flash component’s status register is non-volatile, then BIOS should issue an atomic
software sequence cycle to unlock the flash part.
3.If both bits 3 (WSR) and 4 (WEWS) are set to 1b, then sequence of 06h 01h 00h is sent to unlock the SPI
flash on EVERY write and erase that Intel Management Engine firmware performs.
4.If bit 3 (WSR) is set to 1b and bit 4 (WEWS) is set to 0b then sequence of 50h 01h 00h is sent to unlock the
SPI flash on EVERY write and erase that Intel
®
ME FW performs.
5.If bit 3 (WSR) is set to 0b and bit 4 (WEWS) is set to 0b or 1b then sequence of 60h is sent to unlock the SPI
flash on EVERY write and erase that Processor or Intel GbE FW performs.
6.The manufacturers information included in the QER list are for guidance purpose. Some manufacturer devices
operate as shown in the table above. Check manufacturer’s datasheet for exact requirements.
Bits Description
31:16
Reserved
15:8
Erase Opcode (EO). This field must be programmed with the Flash erase instruction opcode that
corresponds to the erase size that is in BES.
7:5
Quad Enable Requirements (QER)
000 = Part does not require a Quad Enable bit to be set, either because Quad is not supported or
because the manufacturer permanently enables Quad capability (e.g., Micron*, Numonyx*).
001 = Part requires bit 9 in status register 2 to be set to enable quad IO. Writing one byte to status
register clears all bits in register 2, therefore status register writes MUST be two bytes. If
the status register is unlocked and SFDP bits WSR or VSCC WSR is 1 then SPI controller can-
not use the quad output, quad IO features of this part because the hardware will automati-
cally write one byte of zeros to status register with every write/erase. (e.g., Winbond*,
AMIC*, Spansion*).
010 = Part requires bit 6 of status register 1 to be set to enable quad IO. If the status register is
unlocked and SFDP WSR bit or VSCC WSR is 1 then flash controller cannot use the quad out-
put, quad IO features of this part because the hardware will automatically write one byte of
zeros to status register with every write/erase (e.g., Macronix*).
011 = Part requires bit 7 of the configuration register to be set to enable Quad (e.g. Atmel*).
100 = Part requires bit 9 in status register 2 to be set to enable quad IO. Writing one byte to the
status register does not clear the second byte (SST*/Microchip*, Winbond*).
Note: Please refer to Table note#6 below for details.
4
Write Enable on Write Status (WEWS)
0 = 50h is the opcode used to unlock the status register on SPI flash if WSR (bit 3) is set to 1b.
1 = 06h is the opcode used to unlock the status register on SPI flash if WSR (bit 3) is set to 1b.
Note: Please refer to Table Note #4 below for a description how this bit is used.
3
Write Status Required (WSR)
0 = No automatic write of 00h will be made to the SPI flash’s status register)
1 = A write of 00h to the SPI flash’s status register will be sent on EVERY write and erase
performed by Intel
®
ME to the SPI flash.
Note: Please refer to Table Note #5 below for a description how this bit is used.
2
Write Granularity (WG).
0 = 1 Byte
1 = 64 Bytes
1:0
Block/Sector Erase Size (BES). This field identifies the erasable sector size for all Flash
components.
00 = 256 Bytes
01 = 4 K Bytes
10 = 8 K Bytes
11 = 64K Bytes