Intel PCH-LP, Руководство по программированию

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86 523462
Intel Confidential
APPENDIX A - Descriptor Configuration
13:12 PCIe* Port Configuration Strap 3 (PCIEPCS3)
These straps set the default value of the PCI Express* port
Configuration 2 register covering PCIe port 6.
11: 1x4
10: 1x2
01: Reserved
00: 1x1
Setting of this field depend on what PCIe port 6
configurations are desired by the board manufacturer.
Only the x4 configuration ("11") has the option of
lane reversal if PCIELR3 is set to ’1’.
Note: This field must be determined by the PCI
Express* port requirements of the design.
The platform hardware designer must
determine this setting.
11:10 PCI Express Port Configuration Strap 2 (PCIEPCS2)
These straps set the default value of the PCI Express port
Configuration 2 register covering PCIe port 5.
"11": 1x4
"10": 1x2
"01": Reserved
"00": 1x1
Setting of this field depend on what PCIe port 5
configurations are desired by the board manufacturer.
Only the x4 configuration ("11") has the option of
lane reversal if PCIELR2 is set to ’1’.
This field must be determined by the PCI Express*
port requirements of the design. The platform
hardware designer must determine this setting.
9:8 SATA Port 0 PCIe Port 6 Lane 3 Mode
(SATAP0_PCIEP6L3_MODE)
00 : Statically assigned to SATA Port 0
01 : Statically assigned to PCIe Port 6 Lane 3
10 : Reserved
11 : Assigned based on the native mode of GPIO34 pin. If
the native mode of GPIO34 pin is a ‘1’, then it is assigned to
SATA Port 0, else it is assigned to PCIe Port 6 Lane 3.
If this soft strap is set to “11” then GPIO34 native
mode is SATA0_PCIE6L3#, else the native mode is
SATA0GP.
7:6 SATA Port 1 PCIe Port 6 Lane 2 Mode
(SATAP1_PCIEP6L2_MODE)
00 : Statically assigned to SATA Port 1
01 : Statically assigned to PCIe Port 6 Lane 2
10 : Reserved
11 : Assigned based on the native mode of GPIO35 pin. If
the native mode of GPIO35 pin is a ‘1’, then it is assigned to
SATA Port 1, else it is assigned to PCIe Port 6 Lane 2.
If this soft strap is set to “11” then GPIO35 native
mode is SATA1_PCIE6L2#, else the native mode is
SATA1GP.
5:4 SATA Port 2 PCIe Port 6 Lane 1 Mode
(SATAP2_PCIEP6L1_MODE)
00 : Statically assigned to SATA Port 2
01 : Statically assigned to PCIe Port 6 Lane 1
10 : Reserved
11 : Assigned based on the native mode of GPIO36 pin. If
the native mode of GPIO36 pin is a ‘1’, then it is assigned to
SATA Port 2, else it is assigned to PCIe Port 6 Lane 1.
If this soft strap is set to “11” then GPIO36 native
mode is SATA1_PCIE6L1#, else the native mode is
SATA2GP.
3:2 SATA Port 3 PCIe Port 6 Lane 0 Mode
(SATAP3_PCIEP6L0_MODE)
00 : Statically assigned to SATA Port 3
01 : Statically assigned to PCIe Port 6 Lane 0
10 : Reserved
11 : Assigned based on the native mode of GPIO37 pin. If
the native mode of GPIO37 pin is a ‘1’, then it is assigned to
SATA Port 3, else it is assigned to PCIe Port 6 Lane 0.
If this soft strap is set to “11” then GPIO37 native
mode is SATA1_PCIE6L0#, else the native mode is
SATA3GP.
1 Backbone Clock Source Select (PLLSRC_PXPXOPIB):
0 = OPI PLL is the source (default)
1 = PCIe PLL is the source.
0 PCIe NAND x1 or x2 Select (PNX1X2S):
0 = NAND Cycle Router configured for PCIe NAND x1
1 = NAND Cycle Router configured for PCIe NAND x2
Bits Description Usage