Intel PCH-LP, Руководство по программированию

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APPENDIX A - Descriptor Configuration
A.7 PCHSTRP5—Strap 5 Record (Flash Descriptor
Records)
Flash Address: FPSBA + 014h Default Value: 00000000h
Size: 32 bits
Default Flash Address: 114h
A.8 PCHSTRP6—Strap 6 Record (Flash Descriptor
Records)
Flash Address: FPSBA + 018h Default Value: 00000000h
Size: 32 bits
A.9 PCHSTRP7—Strap 7 Record (Flash Descriptor
Records)
Flash Address: FPSBA + 01Ch Default Value: 00000000h Size:
32 bits
A.10 PCHSTRP8—Strap 8 Record (Flash Descriptor
Records)
Flash Address: FPSBA + 020h Size: 32 bits
Default Flash Address: 120h
Bits Description Usage
31:0 Reserved, set to ’0’
Bits Description Usage
31:0 Reserved, set to ’0’
Bits Description Usage
31:0 Intel
®
ME SMBus Subsystem Vendor and Device ID
(MESMA2UDID):
MESMAUDID[15:0] - Subsystem Vendor ID
MESMAUDID[31:16] - Subsystem Device ID
The values contained in MESMAUDID[15:0] and
MESMAUDID[31:16] are provided as bytes 8-9 and 10-11 of
the data payload to an external master when it initiates a
Directed GET UDID Block Read Command to the Alert
Sending Device ASD's address.
This bit must only be set to ’1’ when there is an ASD
(Alert Sending Device) attached to SMBus and when
MESMASDEN(PCHSTRP2 bit 8) is set to ’1’. This is
only applicable in platforms using Intel
®
AMT. Set this
if you want to add a 4 byte payload to an external
master when a GET UDID Block read command is
made to Intel ME SMBus ASD’s address.
Bits Description Usage
31:0 Reserved, set to ’0’