Intel PCH-LP, Руководство по программированию

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Descriptor Overview
4.1.1.4 FLMAP2—Flash Map 2 Register
(Flash Descriptor Records)
Memory Address: FDBAR + 01Ch Size: 32 bits
4.1.2 Flash Descriptor Component Section
4.1.2.1 FLCOMP—Flash Components Register
(Flash Descriptor Records)
The following section of the Flash Descriptor is used to identify the different SPI Flash
Components and their capabilities.
Memory Address: FCBA + 000h Size: 32 bits
Bits Description
31:24
Register Init Length (RIL): Identifies the 1's based number of register initialization entries. If this
field is set to 0, then there are no Register Init entries to send. Each register init entry is 2DW in
length. Set this field to 08h.
23:16 Reserved. Set this field to 21h.
15:08
CPU Strap Length (CPUSL). Identifies the 1's based number of Dwords of Processor Straps to be
read, up to 255 DWs (1KB) max. A setting of all 0's indicates there are no Processor DW straps.
Set this field to 01h.
7:0
Flash CPU Strap Base Address (FCPUSBA). This identifies address bits [11:4] for the Processor
Strap portion of the Flash Descriptor. Bits [24:12] and bits [3:0] are 0.
Set this field to 20h. This will define FCPUSBA as 200h
Bits Description
31 Reserved
30
Dual Output Fast Read Support
0 : Dual Output Fast Read is not supported
1 : Dual Output Fast Read is supported
Notes:
1.If the Dual Output Fast Read Support bit is set to 1b, the Dual Output Fast Read instruction is
issued in all cases where the Fast Fread would have been issue
2.The Frequencies supported for the Dual Output Fast Read are the same as those supported by the
Fast Read Instruction
3.If more than one Flash component exists, this field can only be set to “1” if both component
support Dual Output Fast Read
4.The Dual output Fast Fead is only supported using the 3Bh opcode and dual read only affect the
read data, not the address phase.
5.this field only has effect if the SFDP parameter table is not detected. If the SDFDP parameter table
is detected, this field is ignored and SFDP discovered parameter is used instead
29:27
Read ID and Read Status Clock Frequency.
000 = 20 MHz
001 = 33 MHz
100 = 50 MHz
All other Settings = Reserved
Notes:
1.If more than one Flash component exists, this field must be set to the lowest common frequency
of the different Flash components.
2.If setting to 50 MHz, ensure flash meets timing requirements defined in Table 3-3