Intel IXP28 Series, Руководство пользователя

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84 Hardware Design Guide
IXP28XX Network Processor
QDR SRAM
4.8 IXDP2800 QDR Implementation Guidelines
The following is a list of QDR SRAM routing topologies that have been implemented on the
IXDP2800 Advanced Development Platform:
•
Simulation shows that no termination is required for two-device “clamshell” topology, as
shown in
Figure 47 .
•
Performance is at 250+ MHz.
4.8.1 Routing for a Four-QDR SRAM Topology
For topologies using four loads during a read, only one SRAM drives the bus, and the stub to the
other SRAM causes a reflection that effectively reduces the data-valid window. The maximum
operating frequency is effectively, approximately 167 MHz.
The following are routing recommendations for four QDR SRAM topologies:
•
Only terminate lines on IXP28XX network processor drives.
•
OUTCLK/OUTCLK_L is 4.5 inches.
•
The x9 devices are recommended for topologies that use four loads, and for 200+ MHz
operations.
•
The x18 devices are recommended for 167+ MHz operations.
Figure 47. QDR SRAM Routing Recommendations
B3418-01
Loopback Clock Length: 7.5"
*
2.0" - 2.25"
0.2" - 0.3"
0.2" - 0.3"
Data, Controller,
SRAM Clks
C[1]
CIN[0]
Intel
®
IXP2800
Network Processor
QDR
SRAM1
QDR
SRAM2
* Note: Loopback clock length is determined from paper analysis. Actual implemented length may vary and
should be determined by performing a detailed timing analysis using extracted layout parasitics.
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