Intel IXP28 Series, Руководство пользователя

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144 Hardware Design Guide
IXP28XX Network Processor
Slowport
On the clock cycle after the read signal is de-asserted from the downstream device, the glue logic
will drive the first byte of data onto the SP_AD bus since the IXP28XX network processor does not
pulse the SP_CP signal to promote the first read. The remaining three bytes of data are shifted out
on the rising edge of the SP_CP signal to complete the 32-bit transfer.
Example 5. 32-bit Read Unpacking Logic Implementation
// control logic for shifting the 32-bit read data back to IXP, 8-bits
// per cycle
assign shift_en = (~sp_oe_l && ~sp_a[1]);
The following Verilog* code depicts an example implementation of the data unpacking logic:
// implementation of pack_cnt control logic, the count is incremented on each
// rising edge of sp_a[0] if shift_en is active
always @(posedge sp_a[0]) begin
if (~rst_l) begin
pack_cnt <= 2'b00;
end
else begin
if (shift_en)begin
pack_cnt <= pa 1;
end
else if (~shift_en) begin
pack_cnt <= 2'b00;
end
end // else: !if(~rst_l)
end // always @ (posedge sp_clk)
// Implementation of read data mux, pack_cnt is used to determine which byte
// should be driven onto the sp_rd_out bus
always @ (pack_cnt) begin
//data is shifted during four consecutive cycles
case (pack_cnt) //synopsis full_case parallel_case
2'b00: sp_rd_out <= #1 data[31:24];
2'b01: sp_rd_out <= #1 data[23:16];
2'b10: sp_rd_out <= #1 data[15:8];
2'b11: sp_rd_out <= #1 data[7:0];
endcase // case(pack_cnt)
end
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