Intel IXP28 Series, Руководство пользователя

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Hardware Design Guide 65
IXP28XX Network Processor
QDR SRAM
4.5 QDR SRAM Routing Rules
4.5.1 QDR Trace Requirements
The most important design detail of the QDR interface is to accurately length-match all signals
from the controller to the pins of the SRAM device. This allows the control and data signals to
reach the pins of the SRAM and the IXP28XX network processor (for read) at the same time. In the
case of read data being returned to the IXP28XX network processor this makes it easy to find a
common data valid window for all signals to be captured by the controller. During initialization of
the QDR channel the DLL in the receive path can be programmed to find a suitable capture clock
to strobe the read data. Refer to the
IXP2800 Hardware Initialization Reference Manual for more
details.
It is important to note here that ALL nets within one signal group must be length matched among
each other to within ±25mils, or preferably to within ±10mils. This is achievable and has been
done. This means that all Address signals must have the same length to within ±25mils and
similarly for the rest of the signal groups. This requirement is more critical in the K-Clock and C-
Clock signals which have to be routed with extreme care.
What is meant by length here is the total length of the net including the package trace length plus
the PCB board trace length from the Driver Die-Pad to the Receiver Die-Pad. This total length on
one net must be matched to the total length of each net in the same group. In essence, the Address
nets must be length matched together, the Data-OUT nets must be matched together, and so on.
However, the length of a Data-OUT net, for example, needs does not need to be matched to an
Address net etc.
A complete listing of package trace lengths for all nets in all groups would be available in a
separate spreadsheet. This spreadsheet can be used to do the length matching of the nets.
The following are QDR trace requirements:
•
All signals must be length-matched from the controller to each QDR SRAM pin.
— For topologies that implement a balance “T” topology, you only account for the length of
one arm of the “T” when performing the length matching.
•
All signal lines must be matched to within 25 mils.
— You must compensate for controller package substrate routing, otherwise signal lines must
be matched to within 25 mils. The package substrate lengths are provided in Section 4.12 .
Note: It is strongly recommended that a simulation analysis of the final layout be performed to ensure all
timing requirements are being satisfied. This will catch any length-matching mistakes that may
have been introduced during trace length matching.
4.5.2 QDR SRAM Address Topology
The Address signals are properly mirrored in the SRAM part. This makes the balanced T-Topology
with matched branches the favorable configuration for Address signals. However, some Address
pins may not lend themselves to be routed as a balanced T-topology. A T-topology with un-
matched branches might become necessary in this case leading to a T-topology with daisy-chain
branches. We recommend to exert every effort to use balanced T-topology for the address with 4
SRAM loads for adequate signal integrity and timing margin.
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