Intel
®
Server Board S5500BC TPS
Functional Architecture
Revision 1.0
Intel order number: E42249-003
19
Error
Severity
System Action
Processor frequency
(speed) not identical
Major
The BIOS detects the error condition and responds as
follows:
Adjusts all processor frequencies to lowest
common denominator.
Continues to boot the system successfully.
If the frequencies for all processors cannot all be adjusted to
be the same, then the BIOS:
Logs the error into the SEL.
Displays “0197: Processor speeds mismatched”
message in the error manager.
Halts the system.
Processor microcode
missing
Fatal
The BIOS detects the error condition and responds as
follows:
Logs the error into the SEL.
Alerts the BMC of the configuration error with an
IPMI command.
Does not disable the processor.
Displays “816x: Processor 0x unable to apply
microcode update” message in the error manager.
Pauses the system for user intervention.
Processor Intel
®
QuickPath Interconnect
speeds not identical
Fatal
The BIOS detects the error condition and responds as
follows:
Logs the error into the system event log (SEL).
Alerts the BMC of the configuration error with an
IPMI command.
Does not disable processor.
Displays “0195: Processor Front Side Bus speed
mismatch detected” message in the error manager.
Halts the system.
3.1.3
Multiple Processor Initialization
Intel
®
IA-32 processors have a microcode-based bootstrap processor (BSP) arbitration protocol.
The BSP starts executing from the reset vector (F000:FFF0h). A processor that does not
perform the role of BSP is referred to as an application processor (AP).
The Intel
®
Server Board S5500BC is a dual-socket server platform based on Intel
®
QuickPath
Interconnect replacing Front Side Bus architecture. At reset, one BSP per processor socket is
selected. However, the BIOS POST Power On Self Test (POST) code requires only one
processor for execution. This requires the BIOS to elect a single system BSP using registers in
