Table of Contents
Intel
®
Server Board S5500BC TPS
Intel order number: E42249-003
Revision 1.0
iv
Table of Contents
1.
Introduction .......................................................................................................................... 1
1.1
Server Board Use Disclaimer .................................................................................. 1
2.
Product Overview ................................................................................................................. 2
2.1
Feature Set .............................................................................................................. 2
2.2
Server Board Layout................................................................................................ 4
2.2.1
Server Board Connector and Component Layout.................................................... 4
2.2.2
Server Board Mechanical Drawing .......................................................................... 6
2.2.3
Intel
®
Light-Guided Diagnostic LED Locations....................................................... 13
2.2.4
External I/O Connector Locations.......................................................................... 14
3.
Functional Architecture ..................................................................................................... 15
3.1
Processor Sub-system........................................................................................... 15
3.1.1
Intel
®
QuickPath Interconnect (QPI) ...................................................................... 16
3.1.2
Processor Population Rules .................................................................................. 17
3.1.3
Multiple Processor Initialization ............................................................................. 19
3.1.4
Turbo Mode ........................................................................................................... 20
3.1.5
Simultaneous Multi-Threading ............................................................................... 20
3.1.6
Enhanced Intel
®
SpeedStep
®
Technology ............................................................. 20
3.1.7
Multi-Core Processor Support ............................................................................... 21
3.1.8
Independent Loading Mechanism (ILM) Back Plate Design Support .................... 21
3.2
Memory Sub-system.............................................................................................. 22
3.2.1
Integrated Memory Controller ................................................................................ 22
3.2.2
DIMM Population Requirements............................................................................ 23
3.2.3
Memory Upgrade Guidelines ................................................................................. 25
3.2.4
Support for Mixed-speed Memory Modules ........................................................... 26
3.2.5
CPU Cores, QPI Links and DDR3 Channels Frequency Configuration................. 26
3.2.6
Memory RAS Features .......................................................................................... 26
3.2.7
Independent Channel Mode .................................................................................. 27
3.2.8
Channel Mirroring Mode ........................................................................................ 27
3.2.9
Lockstep Channel Mode ........................................................................................ 27
3.2.10
Demand and Patrol Scrub ..................................................................................... 28
3.3
Intel
®
I/O Hub (IOH) 5500 chipset.......................................................................... 28
3.3.1
PCI Express* Gen 2............................................................................................... 29
