Errata
34
Specification Update
AN50.
Premature Execution of a Load Operation Prior to Exception Handler
Invocation
Problem:
If any of the below circumstances occur it is possible that the load portion of the
instruction will have executed before the exception handler is entered.
1.
If an instruction that performs a memory load causes a code segment limit
violation
2.
If a waiting X87 floating-point instruction or MMX™ technology (MMX) instruction
that performs a memory load has a floating-point exception pending
3.
If an MMX or SSE/SSE2/SSE3/SSSE3 extensions (SSE) instruction that performs a
memory load and has either CR0.EM=1 (Emulation bit set), or a floating-point
Top-of-Stack (FP TOS) not equal to 0, or a DNA exception pending
Implication:
In normal code execution where the target of the load operation is to write back
memory there is no impact from the load being prematurely executed, nor from the
restart and subsequent re-execution of that instruction by the exception handler. If
the target of the load is to uncached memory that has a system side-effect, restarting
the instruction may cause unexpected system behavior due to the repetition of the
side-effect. Particularly, while CR0.TS [bit 3] is set, a MOVD/MOVQ with MMX/XMM
register operands may issue a memory load before getting the DNA exception.
Workaround:
Code which performs loads from memory that has side-effects can effectively
workaround this behavior by using simple integer-based load instructions when
accessing side-effect memory and by ensuring that all code is written such that a code
segment limit violation cannot occur as a part of reading from side-effect memory.
Status:
For the steppings affected, see the
AN51.
Performance Monitoring Events for Retired Instructions (C0H) May
Not Be Accurate
Problem:
The INST_RETIRED performance monitor may miscount retired instructions as follows:
•
Repeat string and repeat I/O operations are not counted when a hardware
interrupt is received during or after the last iteration of the repeat flow.
•
VMLAUNCH and VMRESUME instructions are not counted.
•
HLT and MWAIT instructions are not counted. The following instructions, if
executed during HLT or MWAIT events, are also not counted:
a) RSM from a C-state SMI during an MWAIT instruction.
b) RSM from an SMI during a HLT instruction.
Implication:
There may be a smaller than expected value in the INST_RETIRED performance
monitoring counter. The extent to which this value is smaller than expected is
determined by the frequency of the above cases.
Workaround:
None identified.
Status:
