Errata
42
Specification Update
AN77.
Performance Monitoring Events for Hardware Prefetch Requests
(4EH) and Hardware Prefetch Request Cache Misses (4FH) May Not
Be Accurate
Problem:
Performance monitoring events that count hardware prefetch requests and prefetch
misses may not be accurate.
Implication:
This erratum may cause inaccurate counting for Hardware Prefetch Requests and
Hardware Prefetch Request Cache Misses.
Workaround:
Erratum can be avoided by placing a guard page (non-present or non-executable
page) as the last page of the segment or after the page that includes the code
segment limit.
Status:
For the steppings affected, see the
AN78.
EFLAGS, CR0, CR4 and the EXF4 Signal May Be Incorrect after
Shutdown
Problem:
When the processor is going into shutdown due to an RSM inconsistency failure,
EFLAGS, CR0 and CR4 may be incorrect. In addition the EXF4 signal may still be
asserted. This may be observed if the processor is taken out of shutdown by NMI#
Implication:
A processor that has been taken out of shutdown may have an incorrect EFLAGS, CR0
and CR4. In addition the EXF4 signal may still be asserted.
Workaround:
None identified.
Status:
For the steppings affected, see the
AN79.
Erratum removed.
AN80.
Store Ordering May Be Incorrect between WC and WP Memory Types
Problem:
According to Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume
3A: System Programming Guide, WP (Write Protected) stores should drain the WC
(Write Combining) buffers in the same way as UC (Uncacheable) memory type stores
do. Due to this erratum, WP stores may not drain the WC buffers.
Implication:
Memory ordering may be violated between WC and WP stores.
Workaround:
None Identified.
Status:
