Errata
Specification Update
23
AN16.
Use of Memory Aliasing with Inconsistent Memory Type May Cause
System Hang
Problem:
Software that implements memory aliasing by having more than one linear addresses
mapped to the same physical page with different cache types may cause the system
to hang. This would occur if one of the addresses is non-cacheable used in code
segment and the other a cacheable address. If the cacheable address finds its way in
instruction cache, and non-cacheable address is fetched in IFU, the processor may
invalidate the non-cacheable address from the fetch unit. Any micro-architectural
event that causes instruction restart will expect this instruction to still be in fetch unit
and lack of it will cause system hang.
Implication:
This erratum has not been observed with commercially available software.
Workaround:
Although it is possible to have a single physical page mapped by two different linear
addresses with different memory types, Intel has strongly discouraged this practice as
it may lead to undefined results. Software that needs to implement memory aliasing
should manage the memory type consistency.
Status:
For the steppings affected, see the
AN17.
Machine Check Exception May Occur When Interleaving Code
between Different Memory Types
Problem:
A small window of opportunity exists where code fetches interleaved between different
memory types may cause a machine check exception. A complex set of micro-
architectural boundary conditions is required to expose this window.
Implication:
Interleaved instruction fetches between different memory types may result in a
machine check exception. The system may hang if machine check exceptions are
disabled. Intel has not observed the occurrence of this erratum while running
commercially available applications or operating systems.
Workaround:
Software can avoid this erratum by placing a serializing instruction between code
fetches between different memory types.
Status:
