Errata
Specification Update
51
AN104.
Erratum removed
AN105.
BIST Failure after Reset
Problem:
The processor may show an erroneous BIST (built-in self test) result in bit [17] of EAX
register when coming out of reset.
Implication:
When this erratum occurs, an erroneous BIST failure will be reported in EAX bit [17].
This failure can be ignored since it is not accurate.
Workaround:
It is possible for BIOS to workaround this erratum by masking off bit [17] of the EAX
register after coming out of reset.
Status:
For the steppings affected, see the
AN106.
Instruction Fetch May Cause a Livelock during Snoops of the L1 Data
Cache
Problem:
A livelock may be observed in rare conditions when instruction fetch causes
multiple level one data cache snoops.
Implication:
Due to this erratum, a livelock may occur. Intel has not observed this erratum with
any commercially available software.
Workaround:
It is possible for BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
