1. Introduction to the Intel FPGA Programmable
Acceleration Card D5005
This guide provides a brief introduction to the Intel
®
FPGA PAC D5005. This guide
provides the instructions for the following procedures:
•
Installing the Open Programmable Acceleration Engine (OPAE) on the host Intel
Xeon
®
Processor to manage and access the Intel FPGA PAC.
— Configuring and flashing the FPGA image and Board Management Controller
images.
— Running the example
hello_afu
in a non-virtualized environment.
The Intel FPGA PAC D5005 is a collection of software, firmware, and tools that allows
both software and RTL developers to take advantage of the power of Intel FPGAs. By
offloading computationally intensive tasks to the FPGA, the acceleration platform frees
the Intel Xeon processor for other critical processing tasks.
Figure 1.
Overview of the Intel FPGA PAC Platform Hardware and Software
Libraries
Application
OPAE Running on Intel Host
PCIe Accelerator Card
Xeon Processor
Intel FPGA
User Developed
PCIe Driver
Provided by Intel
FPGA Interface
Manager (FIM)
Provided by Intel
User, Intel, and
Third Party
Open Programmable
Acceleration Engine (OPAE)
Provided by Intel
Accelerator Function (AF)
User, Intel, and Third-Party
IP Plugs into AFU Slot
FIM
AFU
Drivers
APIs
UG-20202 | 2019.08.05
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