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Errata

Intel

Core

™

2 Duo Processor

Specification Update

internal conditions, it is possible to have an ordering violation between

memory store and load operations.

Implication:

Due to this erratum, proper load/store ordering may not be followed when

multiple logical processors are accessing the same data that crosses a

cacheline boundary without serialization.

Workaround:

It is possible for the BIOS to contain a workaround for this erratum.

Status:

For the steppings affected, see the Summary Tables of Changes.

AW75.

Unsynchronized Cross-Modifying Code Operations Can Cause

Unexpected Instruction Execution Results

Problem:

The act of one processor, or system bus master, writing data into a currently

executing code segment of a second processor with the intent of having the

second processor execute that data as code is called cross-modifying code

(XMC). XMC that does not force the second processor to execute a

synchronizing instruction, prior to execution of the new code, is called

unsynchronized XMC.

Software using unsynchronized XMC to modify the instruction byte stream of

a processor can see unexpected or unpredictable execution behavior from the

processor that is executing the modified code.

Implication:

In this case, the phrase "unexpected or unpredictable execution behavior"

encompasses the generation of most of the exceptions listed in the

Intel

Architecture Software Developer's Manual Volume 3: System Programming

Guide

, including a General Protection Fault (GPF) or other unexpected

behaviors. In the event that unpredictable execution causes a GPF the

application executing the unsynchronized XMC operation would be terminated

by the operating system.

Workaround:

In order to avoid this erratum, programmers should use the XMC

synchronization algorithm as detailed in the

Intel Architecture Software

Developer's Manual Volume 3: System Programming Guide

, Section: Handling

Self- and Cross-Modifying Code.

Status:

For the steppings affected, see the Summary Tables of Changes.

AW76.

A Page Fault May Not be Generated When the PS bit is set to “1” in a

PML4E or PDPTE

Problem:

On processors supporting Intel® 64 architecture, the PS bit (Page Size, bit 7)

is reserved in PML4Es and PDPTEs. If the translation of the linear address of a

memory access encounters a PML4E or a PDPTE with PS set to 1, a page fault

should occur. Due to this erratum, PS of such an entry is ignored and no page

fault will occur due to its being set.

Implication:

Software may not operate properly if it relies on the processor to deliver page

faults when reserved bits are set in paging-structure entries.

Содержание CORE 2 DUO E7000 - UPDATE 7-2010

Страница 1: ...775 land LGA Package July 2010 Notice The Intel CoreTM 2 Duo processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications Curren...

Страница 2: ...64 Processor will not operate including 32 bit operation without an Intel 64 enabled BIOS Performance will vary depending on your hardware and software configurations See http www intel com technolog...

Страница 3: ...ate 3 Contents Contents 3 Revision History 4 Preface 6 Summary Tables of Changes 8 Identification Information 14 Component Identification Information 15 Errata 18 Specification Changes 48 Specificatio...

Страница 4: ...3 and replaced with a new erratum Added Errata AW58 AW60 Jul 16th 2008 007 Included E7300 processor on M0 stepping Included E8600 processor on E0 stepping Included E0 stepping information Added new Er...

Страница 5: ...Processor Specification Update 5 Revision Number Description Date 017 Added Errata AW77 and AW78 July 15th 2009 018 Added Errata AW79 March 16th 2010 019 Added Errata AW80 Removed Item Numbering Secti...

Страница 6: ...may also contain information that has not been previously published Affected Documents Document Title Document Number Intel Core 2 Duo Processor E8000 and E7000 Series Datasheet 318732 Rev 006 Relate...

Страница 7: ...ing must assume that all errata documented for that stepping are present on all devices Specification Changes are modifications to the current published specifications These changes will be incorporat...

Страница 8: ...ification Changes as noted This table uses the following notations Codes Used in Summary Table Stepping X Erratum Specification Change or Clarification that applies to this stepping No mark or Blank B...

Страница 9: ...X X X X No Fix A REP STOS MOVS to a MONITOR MWAIT Address Range May Prevent Triggering of the Monitoring Hardware AW10 X X X X No Fix Performance Monitoring Event MISALIGN_MEM_REF May Over Count AW11...

Страница 10: ...t Locked Stores May not Trigger the Monitoring Hardware AW30 X X X X No Fix Programming the Digital Thermal Sensor DTS Threshold May Cause Unexpected Thermal Interrupts AW31 X X X X No Fix Writing Sha...

Страница 11: ...ected Processor Behavior AW49 X X Fixed RSM Instruction Execution under Certain Conditions May Cause Processor Hang or Unexpected Instruction Execution Results AW50 X X X X No Fix Benign Exception aft...

Страница 12: ...ception Interrupt Occurs in 64 bit Mode AW71 X X No Fix The XRSTOR Instruction May Fail to Cause a General Protection Exception AW72 X X No Fix The XSAVE Instruction May Erroneously Set Reserved Bits...

Страница 13: ...Processor Specification Update 13 Number SPECIFICATION CLARIFICATIONS AW1 Clarification of TRANSLATION LOOKASIDE BUFFERS TLBS Invalidation Number DOCUMENTATION CHANGES There are no Documentation Chan...

Страница 14: ...Identification Information 14 Intel Core 2 Duo Processor Specification Update Identification Information Figure 1 Processor Package Example...

Страница 15: ...r within the processor s family 3 The Processor Type specified in bits 13 12 indicates whether the processor is an original OEM processor an OverDrive processor or a dual processor capable of being us...

Страница 16: ...E8400 3 00 GHz 1333 MHz 775 land LGA 1 2 3 4 5 6 7 8 9 10 11 12 13 SLAPK C0 6 MB 2 x 3MB 10676h E8500 3 16 GHz 1333 MHz 775 land LGA 1 2 3 4 5 6 7 8 9 10 11 12 13 SLB9Y R0 3 MB 1067Ah E7400 2 80 GHz...

Страница 17: ...support Thermal Monitor 2 TM2 feature 9 These parts have PECI enabled 10 These parts have Enhanced Intel SpeedStep Technology EIST enabled 11 These parts have Extended HALT State C1E enabled 12 These...

Страница 18: ...ame results as if it had initially completed without a page fault Workaround If the page fault handler inspects the arithmetic portion of the saved EFLAGS value then system software should perform a s...

Страница 19: ...oral data may observe data in wrong program order Workaround Software that conforms to the Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A section Buffering of Write Combining M...

Страница 20: ...storage of a PEBS record in the PEBS buffer The information in the PEBS record represents the state of the next instruction to be executed following the counter overflow Due to this erratum if the co...

Страница 21: ...steppings affected see the Summary Tables of Changes AW10 Performance Monitoring Event MISALIGN_MEM_REF May Over Count Problem Performance monitoring event MISALIGN_MEM_REF 05H is used to count the n...

Страница 22: ...gister TPR that lowers the APIC priority the interrupt masking operation may take effect before the actual priority has been lowered This may cause interrupts whose priority is lower than the initial...

Страница 23: ...be a memory ordering violation Workaround Software should avoid crossing page boundaries from WB or WC memory type to UC WP or WT memory type within a single REP MOVS or REP STOS instruction that will...

Страница 24: ...tus For the steppings affected see the Summary Tables of Changes AW19 Store Ordering May be Incorrect between WC and WP Memory Types Problem According to Intel 64 and IA 32 Intel Architecture Software...

Страница 25: ...system side effect restarting the instruction may cause unexpected system behavior due to the repetition of the side effect Particularly while CR0 TS bit 3 is set a MOVD MOVQ with MMX XMM register op...

Страница 26: ...eat prefix and count greater than or equal to 248 may terminate early Early termination may result in one of the following The last iteration not being executed Signaling of a canonical limit fault GP...

Страница 27: ...serviced before higher priority interrupts Implication Software may observe MF being serviced before higher priority interrupts Workaround None identified Status For the steppings affected see the Su...

Страница 28: ...ent or O S timer tick in the case where the monitored address is written by a locked store which is split across cache lines Workaround Do not use locked stores that span cache lines in the monitored...

Страница 29: ...ccur above the 4G limit 0ffffffffh Status For the steppings affected see the Summary Tables of Changes AW33 An Asynchronous MCE During a Far Transfer May Corrupt ESP Problem If an asynchronous machine...

Страница 30: ...uction Due to this erratum a non enabled breakpoint triggered on step 1 or step 2 may be reported in B0 B3 after the breakpoint occurs in step 4 Implication Due to this erratum B0 B3 bits in DR6 may b...

Страница 31: ...e observed in rare conditions when instruction fetch causes multiple level one data cache snoops Implication Due to this erratum a livelock may occur Intel has not observed this erratum with any comme...

Страница 32: ...synchronization Status For the steppings affected see the Summary Tables of Changes AW41 VM Exit with Exit Reason TPR Below Threshold Can Cause the Blocking by MOV POP SS and Blocking by STI Bits to b...

Страница 33: ...nges AW43 VM Exit Caused by a SIPI Results in Zero to be Saved to the Guest RIP Field in the VMCS Problem If a logical processor is in VMX non root operation and in the wait for SIPI state an occurren...

Страница 34: ...VNTDQA are mixed with non streaming loads that split across cache lines the processor may hang Implication Under the scenario described above the processor may hang Intel has not observed this erratum...

Страница 35: ...te of Read Write R W or User Supervisor U S or Present P Bits without TLB Shootdown May Cause Unexpected Processor Behavior Problem Updating a page table entry by changing R W U S or P bits even when...

Страница 36: ...e Check Exception or a System Hang Problem Under a rare set of timing conditions and address alignment of instructions in a short nested loop sequence software that contains multiple conditional jump...

Страница 37: ...may contain incorrect values after any of the following Either STPCLK NMI NonMaskable Interrupt or external interrupts CMP or TEST instructions with an uncacheable memory operand followed by a conditi...

Страница 38: ...eveloper s Manual Volume 3B System Programming Guide Status For the steppings affected see the Summary Tables of Changes AW56 A VM Exit Occuring in IA 32e Mode May Not Produce a VMX Abort When Expecte...

Страница 39: ...tion will extend beyond the deassertion of the RESET signal for a short duration maximum of one millisecond Implication When this erratum occurs on a platform designed to support PSI the voltage regul...

Страница 40: ...VM entry It is necessary to do this before every VM entry because each VM exit will save that bit as 1 This workaround prevents the VM entry failure and sets the FREEZE_WHILE_SMM_EN bit in the IA32_D...

Страница 41: ...ur due to the unexpected non speculative accesses to these memory locations Workaround It is possible for the BIOS to contain a workaround for this erratum Status For the steppings affected see the Su...

Страница 42: ...atum PECI Platform Environment Control Interface will not be enabled as expected by the software In addition due to this erratum processor features reported in ECX following execution of leaf 1 of CPU...

Страница 43: ...the Summary Tables of Changes AW70 LBR BTS BTM May Report a Wrong Address when an Exception Interrupt Occurs in 64 bit Mode Problem An exception interrupt event should be transparent to the LBR Last...

Страница 44: ...absence of this erratum Workaround It is possible for the BIOS to contain a partial workaround for this erratum that prevents XSAVE from setting HEADER XSTATE_BV reserved bits To ensure compatibility...

Страница 45: ...modified code Implication In this case the phrase unexpected or unpredictable execution behavior encompasses the generation of most of the exceptions listed in the Intel Architecture Software Develop...

Страница 46: ...n control set to 1 a VM exit with exit reason NMI window should occur before execution of any instruction if there is no virtual NMI blocking no blocking of events by MOV SS and no blocking of events...

Страница 47: ...rwrite the Value for the IA32_DEBUGCTL MSR Specified in the VM Entry MSR Load Area Problem Following a successful VM entry with the load debug controls VM entry control set to 1 the IA32_DEBUGCTL MSR...

Страница 48: ...es listed in this section apply to the following documents Intel Core 2 Duo Processor E8000 and E7000 Series Datasheet Intel 64 and IA 32 Architectures Software Developer s Manual volumes 1 2A 2B 3A a...

Страница 49: ...cture caches such as the page directory cache which Intel processors implement This information is needed to aid operating systems in managing page table structure invalidations properly Intel will up...

Страница 50: ...tion Changes will be incorporated into a future version of the appropriate processor documentation Note Documentation changes for Intel 64 and IA 32 Architectures Software Developer s Manual volumes 1...

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