Intel CORE 2 DUO E7000 - UPDATE 7-2010, Спецификация

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Errata
34 Intel
®
Core
™
2 Duo Processor
Specification Update
Status:
For the steppings affected, see the Summary Tables of Changes.
AW44. NMIs May Not Be Blocked by a VM-Entry Failure
Problem:
The Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume
3B: System Programming Guide, Part 2 specifies that, following a VM-entry
failure during or after loading guest state, “the state of blocking by NMI is
what it was before VM entry.” If non-maskable interrupts (NMIs) are blocked
and the “virtual NMIs” VM-execution control set to 1, this erratum may result
in NMIs not being blocked after a VM-entry failure during or after loading
guest state.
Implication:
VM-entry failures that cause NMIs to become unblocked may cause the
processor to deliver an NMI to software that is not prepared for it.
Workaround:
VMM software should configure the virtual-machine control structure (VMCS)
so that VM-entry failures do not occur.
Status:
For the steppings affected, see the Summary Tables of Changes.
AW45. Partial Streaming Load Instruction Sequence May Cause the Processor
to Hang
Problem:
Under some rare conditions, when multiple streaming load instructions
(MOVNTDQA) are mixed with non-streaming loads that split across cache
lines, the processor may hang.
Implication:
Under the scenario described above, the processor may hang. Intel has not
observed this erratum with any commercially available software.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
However, streaming behavior may be re-enabled by setting bit 5 to 1 of the
MSR at address 0x21 for software development or testing purposes. If this bit
is changed, then a read-modify-write should be performed to preserve other
bits of this MSR. When the streaming behavior is enabled and using
streaming load instructions, always consume a full cache line worth of data
and/or avoid mixing them with non-streaming memory references. If
streaming loads are used to read partial cache lines, and mixed with non-
streaming memory references, use fences to isolate the streaming load
operations from non-streaming memory operations.
Status:
For the steppings affected, see the Summary Tables of Changes.
AW46. Self/Cross Modifying Code May Not be Detected or May Cause a
Machine Check Exception
Problem:
If instructions from at least three different ways in the same instruction cache
set exist in the pipeline combined with some rare internal state, self-
modifying code (SMC) or cross-modifying code may not be detected and/or
handled.