Errata
Intel
®
Core
™
2 Duo Processor
Specification Update
31
AW37.
Performance Monitoring Event IA32_FIXED_CTR2 May Not Function
Properly when Max Ratio is a Non-Integer Core-to-Bus Ratio
Problem:
Performance Counter IA32_FIXED_CTR2 (MSR 30BH) event counts CPU
reference clocks when the core is not in a halt state. This event is not
affected by core frequency changes (e.g., P states, TM2 transitions) but
counts at the same frequency as the Time-Stamp Counter
IA32_TIME_STAMP_COUNTER (MSR 10H). Due to this erratum, the
IA32_FIXED_CTR2 will not function properly when the non-integer core-to-
bus ratio multiplier feature is used and when a non-zero value is written to
IA32_ FIXED_CTR2. Non-integer core-to-bus ratio enables additional
operating frequencies. This feature can be detected by IA32_PLATFORM_ID
(MSR 17H) bit [23].
Implication:
The Performance Monitoring Event IA32_FIXED_CTR2 may result in an
inaccurate count when the non-integer core-to-bus multiplier feature is used.
Workaround:
If writing to IA32_FIXED_CTR2 and using a non-integer core-to-bus ratio
multiplier, always write a zero.
Status:
For the steppings affected, see the Summary Tables of Changes.
AW38.
Instruction Fetch May Cause a Livelock During Snoops of the L1 Data
Cache
Problem:
A livelock may be observed in rare conditions when instruction fetch causes
multiple level one data cache snoops.
Implication:
Due to this erratum, a livelock may occur. Intel has not observed this
erratum with any commercially available software.
Workaround:
It is possible for BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AW39.
Use of Memory Aliasing with Inconsistent Memory Type may Cause a
System Hang or a Machine Check Exception
Problem:
Software that implements memory aliasing by having more than one linear
addresses mapped to the same physical page with different cache types may
cause the system to hang or to report a machine check exception (MCE). This
would occur if one of the addresses is non-cacheable and used in a code
segment and the other is a cacheable address. If the cacheable address finds
its way into the instruction cache, and the non-cacheable address is fetched
in the IFU, the processor may invalidate the non-cacheable address from the
fetch unit. Any micro-architectural event that causes instruction restart will
be expecting this instruction to still be in the fetch unit and lack of it will
cause a system hang or an MCE.
Implication:
This erratum has not been observed with commercially available software.
Workaround:
Although it is possible to have a single physical page mapped by two different
linear addresses with different memory types, Intel has strongly discouraged
