Intel CORE 2 DUO E7000 - UPDATE 7-2010, Спецификация

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Errata
26 Intel
®
Core
™
2 Duo Processor
Specification Update
Implication:
There may be a smaller than expected value in the INST_RETIRED
performance monitoring counter. The extent to which this value is smaller
than expected is determined by the frequency of the above cases.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AW23. Returning to Real Mode from SMM with EFLAGS.VM Set May Result in
Unpredictable System Behavior
Problem:
Returning back from SMM mode into real mode while EFLAGS.VM is set in
SMRAM may result in unpredictable system behavior.
Implication:
If SMM software changes the values of the EFLAGS.VM in SMRAM, it may
result in unpredictable system behavior. Intel has not observed this behavior
in commercially available software.
Workaround:
SMM software should not change the value of EFLAGS.VM in SMRAM.
Status:
For the steppings affected, see the Summary Tables of Changes.
AW24. CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater or Equal
to 2
48
May Terminate Early
Problem:
In 64-bit Mode CMPSB, LODSB, or SCASB executed with a repeat prefix and
count greater than or equal to 2
48
may terminate early. Early termination may
result in one of the following.
• The last iteration not being executed
•
Signaling of a canonical limit fault (#GP) on the last iteration
Implication:
While in 64-bit mode, with count greater or equal to 2
48
, repeat string
operations CMPSB, LODSB or SCASB may terminate without completing the
last iteration. Intel has not observed this erratum with any commercially
available software.
Workaround:
Do not use repeated string operations with RCX greater than or equal to 2
48
.
Status:
For the steppings affected, see the Summary Tables of Changes.
AW25. Writing the Local Vector Table (LVT) when an Interrupt is Pending
May Cause an Unexpected Interrupt
Problem:
If a local interrupt is pending when the LVT entry is written, an interrupt may
be taken on the new interrupt vector even if the mask bit is set.
Implication:
An interrupt may immediately be generated with the new vector when a LVT
entry is written, even if the new LVT entry has the mask bit set. If there is
no Interrupt Service Routine (ISR) set up for that vector the system will GP
fault. If the ISR does not do an End of Interrupt (EOI) the bit for the vector
will be left set in the in-service register and mask all interrupts at the same or
lower priority.