Summary Tables of Changes
10
Intel
®
Core
™
2 Duo Processor
Specification Update
NO
C0
M0
E0
R0
Plan
ERRATA
AW20
X
X
X
X
No Fix
EFLAGS, CR0, CR4 and the EXF4 Signal May be Incorrect
after Shutdown
AW21
X
X
X
X
No Fix
Premature Execution of a Load Operation Prior to Exception
Handler Invocation
AW22
X
X
X
X
No Fix
Performance Monitoring Events for Retired Instructions
(C0H) May Not Be Accurate
AW23
X
X
X
X
No Fix
Returning to Real Mode from SMM with EFLAGS.VM Set
May Result in Unpredictable System Behavior
AW24
X
X
X
X
No Fix
CMPSB, LODSB, or SCASB in 64-bit Mode with Count
Greater or Equal to 2
48
May Terminate Early
AW25
X
X
X
X
No Fix
Writing the Local Vector Table (LVT) when an Interrupt is
Pending May Cause an Unexpected Interrupt
AW26
X
X
X
X
No Fix
Pending x87 FPU Exceptions (#MF) Following STI May Be
Serviced Before Higher Priority Interrupts
AW27
X
X
X
X
No Fix
VERW/VERR/LSL/LAR Instructions May Unexpectedly
Update the Last Exception Record (LER) MSR
AW28
X
X
X
X
No Fix
INIT Does Not Clear Global Entries in the TLB
AW29
X
X
X
X
No Fix
Split Locked Stores May not Trigger the Monitoring
Hardware
AW30
X
X
X
X
No Fix
Programming the Digital Thermal Sensor (DTS) Threshold
May Cause Unexpected Thermal Interrupts
AW31
X
X
X
X
No Fix
Writing Shared Unaligned Data that Crosses a Cache Line
without Proper Semaphores or Barriers May Expose a
Memory Ordering Issue
AW32
X
X
X
X
No Fix
General Protection (#GP) Fault May Not Be Signaled on
Data Segment Limit Violation above 4-G Limit
AW33
X
X
X
X
No Fix
An Asynchronous MCE During a Far Transfer May Corrupt
ESP
AW34
X
X
X
X
Plan Fix
CPUID Reports Architectural Performance
Monitoring Version 2 is Supported, When Only Version 1
Capabilities are Available
AW35
X
X
X
X
No Fix
B0-B3 Bits in DR6 May Not be Properly Cleared After Code
Breakpoint
AW36
X
X
X
X
No Fix
An xTPR Update Transaction Cycle, if Enabled, May be
Issued to the FSB after the Processor has Issued a Stop-
Grant Special Cycle
AW37
X
X
Fixed
Performance Monitoring Event IA32_FIXED_CTR2 May Not
Function Properly when Max Ratio is a Non-Integer Core-
to-Bus Ratio
AW38
X
X
X
X
No Fix
Instruction Fetch May Cause a Livelock During Snoops of
the L1 Data Cache
AW39
X
X
X
X
No Fix
Use of Memory Aliasing with Inconsistent Memory Type
may Cause a System Hang or a Machine Check Exception
