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Datasheet

Features

behavior.If RESET# is driven active while the processor is in the Sleep state, and held

active as specified in the RESET# pin specification, then the processor will reset itself,

ignoring the transition through the Stop-Grant state.

If RESET# is driven active while the processor is in the Sleep state, the SLP# and

STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure

the processor correctly executes the Reset sequence.

While in the Sleep state, the processor is capable of entering an even lower power

state, the Deep Sleep state, by asserting the DPSLP# pin (See Section 7.2.6). While

the processor is in the Sleep state, the SLP# pin must be deasserted if another

asynchronous FSB event needs to occur. PECI is not available and will not respond

while in the Sleep State. Refer to the appropriate Thermal and Mechanical Design

Guidelines (see

Section 1.2

) for guidance on how to ensure PECI thermal data is

available when the Sleep State is enabled.

6.2.6

Deep Sleep State

The Deep Sleep state is entered through assertion of the DPSLP# pin while in the Sleep

state. BCLK may be stopped during the Deep Sleep state for additional platform level

power savings. BCLK stop/restart timings on appropriate chipset-based platforms with

the CK505 clock chip are as follows:

• Deep Sleep entry: the system clock chip may stop/tristate BCLK within two BCLKs

of DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep.

• Deep Sleep exit: the system clock chip must drive BCLK to differential DC levels

within 2-3 ns of DPSLP# deassertion and start toggling BCLK within 10 BCLK

periods.

To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be restarted

after DPSLP# deassertion as described above. A period of 15 microseconds (to allow for

PLL stabilization) must occur before the processor can be considered to be in the Sleep

state. Once in the Sleep state, the SLP# pin must be deasserted to re-enter the Stop-

Grant state.

While in the Deep Sleep state the processor is incapable of responding to snoop

transactions or latching interrupt signals. No transitions of signals are allowed on the

FSB while the processor is in the Deep Sleep state. When the processor is in the Deep

Sleep state it will not respond to interrupts or snoop transactions. Any transition on an

input signal before the processor has returned to the Stop-Grant state will result in

unpredictable behavior. PECI is not available and will not respond while in the Deep

Sleep State. Refer to the appropriate Thermal and Mechanical Design Guidelines (see

Section 1.2

) for guidance on how to ensure PECI thermal data is available when the

Deep Sleep State is enabled.

6.2.7

Deeper Sleep State

The Deeper Sleep state is similar to the Deep Sleep state but the core voltage is

reduced to a lower level. The Deeper Sleep state is entered through assertion of the

DPRSTP# pin while in the Deep Sleep state. Exit from Deeper Sleep is initiated by

DPRSTP# deassertion. PECI is not available and will not respond while in the Deeper

Sleep State. Refer to the appropriate Thermal and Mechanical Design Guidelines (see

Section 1.2

) for guidance on how to ensure PECI thermal data is available when the

Deeper Sleep State is enabled.

Содержание BX80571E5300 - Pentium 2.6 GHz Processor

Страница 1: ...Document Number 320467 002 Intel Pentium Dual Core Processor E5000 Series Datasheet December 2008...

Страница 2: ...ucts processor_number for details Over time processor numbers will increment based on changes in clock speed cache FSB or other features and increments are not intended to represent proportional or qu...

Страница 3: ...l Interface PECI DC Specifications 25 2 7 3 2 GTL Front Side Bus Specifications 26 2 8 Clock Specifications 27 2 8 1 Front Side Bus Clock BCLK 1 0 and Processor Clocking 27 2 8 2 FSB Frequency Select...

Страница 4: ...Grant State 88 6 2 4 Extended HALT Snoop State HALT Snoop State Extended Stop Grant Snoop State and Stop Grant Snoop State 88 6 2 4 1 HALT Snoop State Stop Grant Snoop State 88 6 2 4 2 Extended HALT S...

Страница 5: ...ile 77 14 Case Temperature TC Measurement Location 78 15 Thermal Monitor 2 Frequency and Voltage Ordering 80 16 Conceptual Fan Control Diagram on PECI Based Platforms 82 17 Processor Low Power State M...

Страница 6: ...l Limits 26 14 GTL Bus Voltage Definitions 27 15 Core Frequency to FSB Multiplier Configuration 28 16 BSEL 2 0 Frequency Table for BCLK 1 0 29 17 Front Side Bus Differential BCLK Specifications 29 18...

Страница 7: ...l Pentium dual core processor E5000 series also includes the Execute Disable Bit capability This feature combined with a supported operating system allows memory to be marked as executable or non exec...

Страница 8: ...8 Datasheet Revision History Revision Number Description Revision Date 001 Initial release August 2008 002 Intel Pentium dual core processor E5300 December 2008...

Страница 9: ...echnologies Execute Disable Bit Intel 64 architecture and Enhanced Intel SpeedStep Technology The processor s front side bus FSB use a split transaction deferred reply protocol The FSB uses Source Syn...

Страница 10: ...that connects the processor to the chipset Also referred to as the processor system bus or the system bus All memory and I O transactions as well as interrupt messages pass between the processor and c...

Страница 11: ...ocument Location Intel Pentium Dual Core Processor E5000 Series Specification Update http download intel com design processor specupdt 320467 pdf Intel Core 2 Duo processor E8000 and E7000 Series and...

Страница 12: ...Introduction 12 Datasheet...

Страница 13: ...ct as a storage well for current when entering an idle condition from a running condition The motherboard must be designed to ensure that the voltage provided to the processor remains within the speci...

Страница 14: ...ore Processor E5000 Series Specification Update for further details on specific valid core frequency and VID values of the processor Note that this differs from the VID employed by the processor durin...

Страница 15: ...1 3875 1 0 0 0 0 0 0 0 0 8125 0 0 1 0 0 1 1 0 1 375 1 0 0 0 0 0 1 0 0 8 0 0 1 0 1 0 0 0 1 3625 1 0 0 0 0 1 0 0 0 7875 0 0 1 0 1 0 1 0 1 35 1 0 0 0 0 1 1 0 0 775 0 0 1 0 1 1 0 0 1 3375 1 0 0 0 1 0 0 0...

Страница 16: ...on the motherboard Unused outputs may be terminated on the motherboard or left unconnected Note that leaving unused outputs unterminated may interfere with some TAP functions complicate debug probing...

Страница 17: ...mits it will either not function or its reliability will be severely degraded Although the processor contains protective circuitry to resist damage from static electric discharge precautions should al...

Страница 18: ...d 1 M minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled into the oscilloscope probe 5 Refer to Table 5 and...

Страница 19: ...ction 2 6 3 2 This table is intended to aid in reading discrete points on Figure 1 3 The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands Voltage regulation fe...

Страница 20: ...tion This overshoot cannot exceed VID VOS_MAX VOS_MAX is the maximum allowable overshoot voltage The time duration of the overshoot event must not exceed TOS_MAX TOS_MAX is the maximum allowable time...

Страница 21: ...forms implement separate power planes for each processor and chipset separate VCC and VTT supplies are necessary This configuration allows for improved noise tolerance as processor frequency increases...

Страница 22: ...ction 4 2 for signal descriptions 2 In processor systems where no debug port is implemented on the system board these signals are used to support a debug port interposer In systems with the debug port...

Страница 23: ...ction 2 7 3 for the DC specifications See Section 6 2 for additional timing requirements for entering and leaving the low power states Table 8 Signal Characteristics Signals with RTT Signals with No R...

Страница 24: ...ecifications is the instantaneous VTT 6 Leakage to VSS with land held at VTT 7 Leakage to VTT with land held at 300 mV NOTES 1 Unless otherwise noted all specifications in this table apply to all proc...

Страница 25: ...el processors chipsets and external thermal monitoring devices The processor contains Digital Thermal Sensors DTS distributed throughout die These sensors are implemented as analog to digital converte...

Страница 26: ...CI behavior does not affect VTT min max specifications Refer to Table 4 for VTT specifications Vin Input Voltage Range 0 15 VTT V Vhysteresis Hysteresis 0 1 VTT V 2 2 The leakage specification applies...

Страница 27: ...ontrols the FSB interface speed as well as the core frequency of the processor As in previous generation processors the processor s core frequency is a multiple of the BCLK 1 0 frequency The processor...

Страница 28: ...pset and clock synthesizer All agents must operate at the same frequency The processor operates at a 800 MHz FSB frequency selected by a 200 MHz BCLK 1 0 frequency Individual processors will only oper...

Страница 29: ...absolute value of the maximum voltage Undershoot is defined as the absolute value of the minimum voltage 5 Measurement taken from differential waveform Table 16 BSEL 2 0 Frequency Table for BCLK 1 0...

Страница 30: ...ase timing difference between successive crossover voltages In other words the largest absolute difference between adjacent clock periods must be less than the period stability T5 BCLK 1 0 Rise and Fa...

Страница 31: ...Electrical Specifications Figure 4 Measurement Points for Differential Clock Waveforms 150 mV 150 mV 0 0V 0 0V Slew_rise 150mV 150mV V_swing Slew _fall Diff T5 BCLK 1 0 rise and fall time through the...

Страница 32: ...Electrical Specifications 32 Datasheet...

Страница 33: ...eader IHS Thermal Interface Material TIM Processor core die Package substrate Capacitors NOTE 1 Socket and motherboard are included for reference and are not part of processor package 3 1 Package Mech...

Страница 34: ...Package Mechanical Specifications 34 Datasheet Figure 6 Processor Package Drawing Sheet 1 of 3...

Страница 35: ...Datasheet 35 Package Mechanical Specifications Figure 7 Processor Package Drawing Sheet 2 of 3...

Страница 36: ...Package Mechanical Specifications 36 Datasheet Figure 8 Processor Package Drawing Sheet 3 of 3...

Страница 37: ...mal to the processor IHS 2 This is the maximum force that can be applied by a heatsink retention clip The clip must also provide the minimum specified load on the processor package 3 These specificati...

Страница 38: ...the components that are included in the package 3 7 Processor Materials Table 21 lists some of the package components and associated materials 3 8 Processor Markings Figure 9 shows the topside marking...

Страница 39: ...r Land Coordinates and Quadrants Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM A...

Страница 40: ...Package Mechanical Specifications 40 Datasheet...

Страница 41: ...tion contains the land listings for the processor The land out footprint is shown in Figure 11 and Figure 12 These figures represent the land out arranged by land number and they show the physical loc...

Страница 42: ...VCC VCC VCC VCC VCC VCC VCC VCC W VCC VCC VCC VCC VCC VCC VCC VCC V VSS VSS VSS VSS VSS VSS VSS VSS U VCC VCC VCC VCC VCC VCC VCC VCC T VCC VCC VCC VCC VCC VCC VCC VCC R VSS VSS VSS VSS VSS VSS VSS V...

Страница 43: ...SS FC39 VTT_OUT_ RIGHT AA VCC VSS A19 VSS A20 PSII VSS FC0 BOOTSELECT Y VCC VSS A18 A16 VSS TESTHI1 TESTHI12 FC44 MSID0 W VCC VSS VSS A14 A15 VSS RSVD MSID1 V VCC VSS A10 A12 A13 FC30 FC29 FC28 U VCC...

Страница 44: ...Clock Input Output ADSTB0 R6 Source Synch Input Output ADSTB1 AD5 Source Synch Input Output BCLK0 F28 Clock Input BCLK1 G28 Clock Input BNR C2 Common Clock Input Output BPM0 AJ2 Common Clock Input Ou...

Страница 45: ...ource Synch Input Output D57 B18 Source Synch Input Output D58 C21 Source Synch Input Output D59 B21 Source Synch Input Output D60 B19 Source Synch Input Output Table 22 Alphabetical Land Assignments...

Страница 46: ...ource Synch Input Output REQ4 J6 Source Synch Input Output RESERVED V2 RESERVED A20 RESERVED AC4 RESERVED AE4 Table 22 Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction RESERVE...

Страница 47: ...er VCC AF19 Power Other VCC AF21 Power Other Table 22 Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction VCC AF22 Power Other VCC AF8 Power Other VCC AF9 Power Other VCC AG11 Po...

Страница 48: ...Other VCC AM15 Power Other VCC AM18 Power Other Table 22 Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction VCC AM19 Power Other VCC AM21 Power Other VCC AM22 Power Other VCC A...

Страница 49: ...Power Other Table 22 Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction VCC T27 Power Other VCC T28 Power Other VCC T29 Power Other VCC T30 Power Other VCC T8 Power Other VCC U2...

Страница 50: ...VSS AB23 Power Other VSS AB24 Power Other VSS AB25 Power Other Table 22 Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction VSS AB26 Power Other VSS AB27 Power Other VSS AB28 Po...

Страница 51: ...VSS AK16 Power Other VSS AK17 Power Other Table 22 Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction VSS AK2 Power Other VSS AK20 Power Other VSS AK23 Power Other VSS AK24 Powe...

Страница 52: ...Other VSS H10 Power Other VSS H11 Power Other Table 22 Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction VSS H12 Power Other VSS H13 Power Other VSS H14 Power Other VSS H17 Po...

Страница 53: ...er Other VSS V7 Power Other VSS W4 Power Other Table 22 Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction VSS W7 Power Other VSS Y2 Power Other VSS Y5 Power Other VSS Y7 Power...

Страница 54: ...ce Synch Input Output B8 VSS Power Other B9 DSTBP0 Source Synch Input Output B10 D10 Source Synch Input Output B11 VSS Power Other B12 D13 Source Synch Input Output B13 COMP8 Power Other Input B14 VSS...

Страница 55: ...VTT Power Other D28 VTT Power Other Table 23 Numerical Land Assignment Land Land Name Signal Buffer Type Direction D29 VTT Power Other D30 VTT Power Other E2 VSS Power Other E3 TRDY Common Clock Input...

Страница 56: ...16 D32 Source Synch Input Output G17 D36 Source Synch Input Output G18 D35 Source Synch Input Output G19 DSTBP2 Source Synch Input Output Table 23 Numerical Land Assignment Land Land Name Signal Buffe...

Страница 57: ...Source Synch Input Output K7 VSS Power Other Table 23 Numerical Land Assignment Land Land Name Signal Buffer Type Direction K8 VCC Power Other K23 VCC Power Other K24 VCC Power Other K25 VCC Power Ot...

Страница 58: ...utput R5 VSS Power Other Table 23 Numerical Land Assignment Land Land Name Signal Buffer Type Direction R6 ADSTB0 Source Synch Input Output R7 VSS Power Other R8 VCC Power Other R23 VSS Power Other R2...

Страница 59: ...ower Other Table 23 Numerical Land Assignment Land Land Name Signal Buffer Type Direction Y3 PSI Asynch CMOS Output Y4 A20 Source Synch Input Output Y5 VSS Power Other Y6 A19 Source Synch Input Output...

Страница 60: ...CC Power Other AD29 VCC Power Other AD30 VCC Power Other Table 23 Numerical Land Assignment Land Land Name Signal Buffer Type Direction AE1 TCK TAP Input AE2 VSS Power Other AE3 FC18 Power Other AE4 R...

Страница 61: ...r Other AG16 VSS Power Other AG17 VSS Power Other AG18 VCC Power Other Table 23 Numerical Land Assignment Land Land Name Signal Buffer Type Direction AG19 VCC Power Other AG20 VSS Power Other AG21 VCC...

Страница 62: ...Asynch CMOS Output AK5 VSS Power Other AK6 FC8 Power Other Table 23 Numerical Land Assignment Land Land Name Signal Buffer Type Direction AK7 VSS Power Other AK8 VCC Power Other AK9 VCC Power Other AK...

Страница 63: ...wer Other AM23 VSS Power Other AM24 VSS Power Other Table 23 Numerical Land Assignment Land Land Name Signal Buffer Type Direction AM25 VCC Power Other AM26 VCC Power Other AM27 VSS Power Other AM28 V...

Страница 64: ...rted in real mode A20M is an asynchronous signal However to ensure recognition of this signal following an Input Output write instruction it must be valid along with the TRDY assertion of the correspo...

Страница 65: ...y the priority agent causes all other agents to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all of its requests...

Страница 66: ...the D 63 0 signals The DBI 3 0 signals are activated when the data on the data bus is inverted If more than half the data bits within a 16 bit group would have been asserted electrically low the bus a...

Страница 67: ...te requires chipset support and may not be available on all platforms NOTE Some processors may not have the Deep Sleep State enabled refer to the Specification Update for specific proceswor and steppi...

Страница 68: ...er IERR Output IERR Internal Error is asserted by a processor as the result of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the processor FSB This transactio...

Страница 69: ...of the first transaction to the end of the last transaction When the priority agent asserts BPRI to arbitrate for ownership of the processor FSB it will wait until it observes LOCK de asserted This en...

Страница 70: ...rocessor to a known state and invalidates its internal caches without writing back any of their contents For a power on Reset RESET must stay active for at least one millisecond after VCC and BCLK hav...

Страница 71: ...ode SMM An SMI Acknowledge transaction is issued and the processor begins program execution from the SMM handler If SMI is asserted during the de assertion of RESET the processor will tri state its ou...

Страница 72: ...alid TMS Input TMS Test Mode Select is a JTAG specification support signal used by debug tools TRDY Input TRDY Target Ready is asserted by the target to indicate that it is ready to receive a write or...

Страница 73: ...y platforms where this land is connected to VSS VSS Input VSS are the ground pins for the processor and should be connected to the system ground plane VSSA Input VSSA provides isolated ground for inte...

Страница 74: ...Land Listing and Signal Descriptions 74 Datasheet...

Страница 75: ...n Power TDP value listed per frequency in Table 25 Thermal solutions not designed to provide this level of thermal capability may affect the long term reliability of the processor and system For more...

Страница 76: ...oltage loadline Specification is ensured by design characterization and not 100 tested 2 Specification is at 34 C TC and minimum voltage loadline Specification is ensured by design characterization an...

Страница 77: ...5 2 45 8 26 56 6 50 67 4 4 46 7 28 57 5 52 68 3 6 47 6 30 58 4 54 69 2 8 48 5 32 59 3 56 70 1 10 49 4 34 60 2 58 71 0 12 50 3 36 61 1 60 71 9 14 51 2 38 62 0 62 72 8 16 52 1 40 62 9 64 73 7 18 53 0 42...

Страница 78: ...manner and interrupt requests are latched and serviced during the time that the clocks are on while the TCC is active When the Thermal Monitor feature is enabled and a high temperature situation exist...

Страница 79: ...perating point represents the normal operating condition for the processor Under this condition the core frequency to FSB multiple used by the processor is that contained in the CLK_GEYSIII_STAT MSR a...

Страница 80: ...cessor IA32_THERM_CONTROL MSR is written to a 1 the processor will immediately reduce its power consumption via modulation starting and stopping of the internal core clock independent of the processor...

Страница 81: ...t maximum sustained current instead of maximum current Systems should still provide proper cooling for the VR and rely on bi directional PROCHOT only as a backup in case of system cooling failure The...

Страница 82: ...utilize the relative temperature value delivered over PECI in conjunction with the TCONTROL MSR value to control or optimize fan speeds Figure 16 shows a conceptual fan control diagram using PECI temp...

Страница 83: ...ion that ensures proper processor operation during the time frame when reliable data is not available via PECI To protect platforms from potential operational or safety issues due to an abnormal condi...

Страница 84: ...Thermal Specifications and Design Considerations 84 Datasheet...

Страница 85: ...option 2 Address signals not identified in this table as configuration options should not be asserted during RESET 3 Disabling of any of the cores within the processors must be handled by configuring...

Страница 86: ...pon the occurrence of SMI INIT or LINT 1 0 NMI INTR RESET will cause the processor to immediately initialize itself Figure 17 Processor Low Power State Machine Normal State Normal Execution Stop Grant...

Страница 87: ...T state when a break event occurs When the processor exits the Extended HALT state it will resume operation at the lower frequency transition the VID to the original value and then change the bus rati...

Страница 88: ...noop on the FSB has been serviced whether by the processor or another agent on the FSB After the snoop is serviced the processor will return to the Stop Grant state or HALT powerdown state as appropri...

Страница 89: ...o differential DC levels within 2 3 ns of DPSLP deassertion and start toggling BCLK within 10 BCLK periods To re enter the Sleep state the DPSLP pin must be deasserted BCLK can be restarted after DPSL...

Страница 90: ...age This allows the processor to run at different core frequencies and voltages to best serve the performance and power requirements of the processor and system Note that the front side bus is not alt...

Страница 91: ...chapter are dimensioned in millimeters and inches in brackets Figure 18 shows a mechanical representation of a boxed processor Note Drawings in this section reflect only the specifications on the Int...

Страница 92: ...h assembled fan heatsink are shown in Figure 19 Side View and Figure 20 Top View The airspace requirements for the boxed processor fan heatsink must also be incorporated into new baseboard and system...

Страница 93: ...12 V power supply A fan power cable will be shipped with the boxed processor to draw power from a power header on the baseboard The power cable connector and pinout are shown in Figure 22 Baseboards m...

Страница 94: ...n Heatsink Power Cable Connector Description Table 29 Fan Heatsink Power and Signal Specifications Description Min Typ Max Unit Notes 12 V 12 volt fan power supply 11 4 12 12 6 V IC Maximum fan steady...

Страница 95: ...ons see Table 25 in chassis that provide good thermal management For the boxed processor fan heatsink to operate properly it is critical that the airflow provided to the fan heatsink is unimpeded Airf...

Страница 96: ...ed Processor Specifications 96 Datasheet Figure 24 Boxed Processor Fan Heatsink Airspace Keepout Requirements side 1 view Figure 25 Boxed Processor Fan Heatsink Airspace Keepout Requirements side 2 vi...

Страница 97: ...ncreases so does fan noise levels Systems should be designed to provide adequate air around the boxed processor fan heatsink that remains cooler then lower set point These set points represented in Fi...

Страница 98: ...ctive fan heat sink solution is connected to an older 3 pin baseboard processor fan header it will default back to a thermistor controlled mode allowing compatibility with existing 3 pin baseboard des...

Страница 99: ...processor The LAI lands plug into the processor socket while the processor lands plug into a socket on the LAI Cabling that is part of the LAI egresses the system to allow an electrical connection bet...

Страница 100: ...Debug Tools Specifications 100 Datasheet...

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