Intel 740, Руководство по конструкции, Страница: 208 / 246

PC SGRAM Specification
18
Revision 0.9
8.0 Essential Functionality for the “PC SGRAM” device
The functionality that are essential for the “PC SGRAM” device are described below:
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Burst Read
•
Burst Write
•
Multi bank access
•
Burst Read with Autoprecharge
•
Burst Write with Autoprecharge
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Burst Read terminated with precharge
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Burst Write terminated with precharge
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Burst Read terminated with another Burst Read/Write
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Burst Write terminated with another Burst Write/Read
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DQM masking
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Fastest command to command delay of 1 clock
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Precharge All command
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Auto Refresh
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CL=2,3
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Burst Length 1,2, 4 & 8
8.1 Burst Read and Burst Write
Burst read and write commands are initiated as shown in the diagram below. The bank first needs to
be activated (if not already activated) through the activate bank command and then the read or write
command should be initiated. Read and write is distinguished by the WE# signal state as shown.
T
RCD
(RAS to CAS delay) must be met to initiate a command after the activate command.
8.2 Multi- bank ping pong access
Two bank ping pong access is described in the following diagram. Another bank can be activated
while the first bank is being accessed as shown. RAS to RAS delay T
RRD
must be met while
activating another bank.
8.3 Read and Write with autoprecharge
Burst reads and writes with auto precharge commands are initiated with autoprecharge if A8/A9 is
to high while the read or write commands are issued.
8.3.1 Precharge Command After a Burst Read
The earliest a precharge command can be issued after a Read command without the loss of data is
CL + BL - 2 clocks. The precharge command can be issued as soon as the tras time is met. The
earliest time that precharge can be issued is shown for the CAS Latency = 3 devices.