Intel 740, Руководство по конструкции, Страница: 194 / 246

PC SGRAM Specification
4
Revision 0.9
2.1 Pin Functional Descriptions (Simplified)
a. See the Truth Table and functional description for detailed information about the functionality
Table 1. Pin Functional Description
Symbol Type Description
a
A[9:0] Input - Synchronous Address. Multiplexed Row and Column Address.
BA Input - Synchronous Bank Address. BA0 and BA1 specify the selected Bank during
AP Input - Synchronous Auto Precharge (Multiplexed with Row Address).
CLK Input - Clock Clock Input
CKE Input - Clock Enable
Activates the CLK signal when high and deactivates when low. By
deactivating the clock, CLKE low initiates the Power Down mode.
CS# Input - Synchronous
Chip Select. Disables or enables the device operation by masking or
enabling all inputs except CLK, CLK#, CKE, DQS, DQ and DM.
RAS# Input - Synchronous Row address strobe.
CAS# Input - Synchronous Column address strobe.
WE# Input - Synchronous Write Enable.
DQM[3:0] Input
DQ Mask. Write data byte mask, Read output byte enables Active high.
Read latency is two cycle from DQM and zero cycle for write. In write
mode it masks the data from being written to the memory array. DM
masking occurs in the same cycle during write operation. Write data byte
mask, Read output byte enables. DQM is synchronous to the clock; thus,
the masking occurs for the whole clock.
DQ[31:0] Input/Output Data IO pins.
DSF Input - Synchronus
DFS: Enables the write per bit and Block write function. This pin has an
internal pull-down resistor.
Vcc, Vss Power pins Supply Pins for the core
VccQ,
VssQ
Power pins Supply Pins for the output buffers