Intel 740, Руководство по конструкции, Страница: 18 / 246

Addin Card Design
2-4 Intel740™ Graphics Accelerator Design Guide
2.1.3.2 Fences
A “fence” is a line routed out of the plane such that a given area is isolated from the rest of the
plane except at a single point of contact, conceptually the “gate” in the fence. A fence will
minimize noise originating from digital signaling onto the analog signals. This provides higher
quality video for both the Bt829B and Bt869. An example of a fenced power plane is shown in
Figure 2-1 . The heavy black line is the routed area. The width of the gate or opening can be up to
75% of the length of the IC in question. The width of the routed fence should conform to the
separation routing between power planes (i.e., 25 mils minimum).
2.1.3.3 Stitching
Power plane “stitching” is required between the VCC3 and VDDQ3 planes. Stitching two isolated
planes together with capacitors allows a current return path for high frequency signals which pass
over split power planes. This helps to eliminate EMI. The six 0.1
µ
F capacitors coupling VCC3 to
VDDQ3 should be spaced evenly if possible. Note the VDDQ3 plane is only near the AGP
connector. An example of stitching is shown in
Figure 2-2 . This figure illustrates the power planes
and, therefore, does not show signal traces between capacitors. The general rule for power plane
stitching is to have a capacitor placed between every four signals crossing the two planes. As an
example, there should be a capacitor, four signals, a capacitor, another four signals, and so forth
ending with a capacitor.
Figure 2-1. Example of Power Plane Separation ("fencing")
Fenced area
(e.g. AVCC)
Plane
(e.g. VCC)
“gate”
Routed “fence”
Overlying Chip
Figure 2-2. Example of Power Plane Stitching
c a p
c a p
c a p
c a p
I C
V D D Q 3
V C C 3