IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -86
LOGIC DIAGRAM
PIN CONFIGURATION
Q213, Q214: K4M563233G (256 Mbit SDRAM)
TX-NR905/NA905
Bank Select
Data Input Register
2M x 32
2M x 32
Se
n
s
e A
M
P
Outp
u
t Buf
fe
r
I/O Contro
l
Column Decoder
Latency & Burst Length
Programming Register
Address Registe
r
Row Buf
fer
Refresh C
ounter
R
ow Decoder
C
ol. Buf
fer
LRAS
LCBR
LCKE
M
Q
D
L
E
W
L
R
B
C
L
S
A
R
L
CLK
CKE
CS
RAS
CAS
WE
DQM
LWE
LDQM
DQi
CLK
ADD
R
B
C
W
L
S
A
C
L
2M x 32
2M x 32
Timing Register
<T
op
V
iew>
5
2
1
6
3
4
8
9
7
F
E
D
C
B
J
H
G
A
#A1 Ball Origin Indicator
M
L
K
R
P
N
K4M563233G-XXXX
SAMSUNG W
eek
FBGA Package