Q211: RTL8100CL (Ethernet Controller with Power Management)
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -78
TX-NR905/NA905
BLOCK DIAGRAM
MII
Interface
Interrupt
Control
Logic
FIFO
Transmit/
Receive
Logic
Interface
Early Interrupt
Control Logic
FIFO
Control
Logic
P
a
ck
et
Ty
pe
Di
s
c
rim
in
a
tor
Power Control Logic
PC
I
Interfac
e
+
R
egi
st
er
Pa
c
k
e
t
L
e
n
g
th
R
e
gi
ster
Early Interrupt
Threshold
Register
EEPROM
Interface
LED Driver
RXIN+
RXIN-
TXO+
TXO -
RXC 25M
25M
TXC 25M
TXD
RXD
TD+
Variable Current
3 Level
Driver
Master
PPL
Adaptive
Equalizer
Peak
Detect
3 Level
Comparator
Control
Voltage
MLT-3
to NRZI
Serial to
Parrallel
ck
Data
Slave
PLL
Parrallel
to Serial
Baseline
Wander
Correction
5B 4B
Decoder
Data
Alignment
Descrambler
4B 5B
Encoder
Scrambler
10/100
half /full
Switch
Logic
10/100M Auto-negotiation
Control Logic
Manchester Coded
Waveform
10M Output Waveform
Shaping
Data Recovery
Receive Low Pass Filter
RXD
RXC 25M
TXD
TXC 25M
TXD10
TXC10
RXD10
RXC10
Link Pulse
MII
Interface
10M
100M
PCI
Interface
MAC
PHY
Transceiver