Document Number: 002-14826 Rev. *G
Page 52 of 65
PRELIMINARY
CYW43903
15.4 LNLDO
Table 28. LNLDO Specifications
Specification
Notes
Min.
Typ.
Max.
Units
Input supply voltage, Vin Min. V
IN
= V
O
+ 0.15V = 1.35V (where V
O
= 1.2V)dropout voltage
requirement must be met under maximum load.
1.3
1.35
1.5
V
Output current
–
0.1
–
150
mA
Output voltage, V
o
Programmable in 25 mV steps. Default = 1.2V.
1.1
1.2
1.275 V
Dropout voltage
At maximum load.
–
–
150
mV
Output voltage DC
accuracy
Includes line/load regulation.
–4
–
+4
%
Quiescent current
No load.
–
44
–
µA
Max. load.
–
970
990
µA
Line regulation
V
in
from (V
o
+ 0.1V) to 1.5V, 150 mA load.
–
–
5
mV/V
Load regulation
Load from 1 mA to 150 mA.
–
0.02
0.05
mV/
mA
Leakage current
Power-down.
–
–
10
µA
Output noise
@30 kHz, 60–150 mA load C
o
= 2.2 µF. @100 kHz, 60–150 mA
load
C
o
= 2.2 µF.
–
–
60
35
nV/rt
Hz nV/
rt Hz
PSRR
@ 1kHz, Input > 1.35V, C
o
= 2.2 µF, V
o
= 1.2V.
20
–
–
dB
LDO turn-on time
LDO turn-on time when the rest of the chip is up.
–
140
180
µs
External output capacitor,
C
o
Total ESR (trace/capacitor): 5 mΩ–240 mΩ.
0.5
1
1. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging.
2.2
4.7
µF
External input capacitor
Only use an external input capacitor at the LDO_VDD1P5 pin if it is
not supplied from the CBUCK output. Total ESR (trace/capacitor): 30
mΩ–200 mΩ.
–
1
2.2
µF
