Infineon Cypress WICED BCM43903, Руководство пользователя

Страница: 52 / 66

Document Number: 002-14826 Rev. *G Page 51 of 65
PRELIMINARY
CYW43903
15.3 CLDO
Table 27. CLDO Specifications
Specification Notes Min. Typ. Max. Units
Input supply voltage, V
in
Min. = 1.2 + 0.15V = 1.35V dropout voltage requirement must be met
under maximum load.
1.3 1.35 1.5 V
Output current – 0.2 – 350 mA
Output voltage, V
o
Programmable in 10 mV steps. Default = 1.2.V. 0.95 1.2 1.26 V
Dropout voltage At max. load. – – 150 mV
Output voltage DC
accuracy
Includes line/load regulation. –4 – +4 %
Quiescent current No load. – 26 – µA
200 mA load. – 2.48 – mA
Line regulation V
in
from (V
o
+ 0.15V) to 1.5V, maximum load. – – 5 mV/V
Load regulation Load from 1 mA to 300 mA. – 0.02 0.05 mV/mA
Leakage current Power down. – 10 40 µA
Bypass mode. – 2 6 µA
PSRR @1 kHz, Vin ≥ 1.35V, C
o
= 4.7 µF. 20 – dB
Start-up time of PMU VIO up and steady. Time from the REG_ON rising edge to the CLDO
reaching 1.2V.
– – 700 µs
LDO turn-on time LDO turn-on time when the rest of the chip is up. – 140 180 µs
External output capacitor,
C
o
Total ESR: 5 mΩ–240 mΩ.
3.76
1
1. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging.
4.7 – µF
External input capacitor Only use an external input capacitor at the LDO_VDD1P5 pin if it is not
supplied from the CBUCK output.
– 1 2.2 µF